Planarizing Semiconductor Surface Using BARC Fill for EDRAM Step Height Reduction
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Solution Overview
Problem
The existing methods for fabricating embedded DRAM (EDRAM) face significant challenges due to large step height differences between memory and logic regions, leading to defects and performance issues during metallization processes, such as routing failures and surface damage, caused by non-uniformity in the conductive layer and residues left at corners.
Innovation Solution
A method involving the formation of a first and second region on a semiconductor wafer, followed by conformal deposition of an interlayer dielectric layer, where a photoresist and bottom anti-reflective coating (BARC) layers are used to planarize the surface, ensuring a uniform thickness across both regions by filling recesses and having similar etching resistance to the interlayer dielectric layer, thereby reducing step height differences and preventing surface anomalies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conformal deposition of interlayer dielectric layer is performed on regions with different thicknesses, then the dielectric layer provides uniform coverage, but large step height differences cause severe defects in subsequent metallization process
Solution Approach 1:
The patent applies preliminary planarization action by forming a fill material in recesses of the substrate before depositing the interlayer dielectric layer. This preliminary filling action creates a more uniform surface topology, allowing the subsequent conformal deposition to achieve both uniform thickness coverage and eliminate step height differences that would cause metallization defects.
2Adaptability or versatility
If large step height difference exists between memory and logic regions, then device integration is achieved, but severe defects such as routing failure occur in metallization process
Solution Approach 1:
The patent applies local quality by selectively filling recesses in specific regions of the substrate with fill material before interlayer dielectric deposition. This local modification creates region-specific planarization that maintains the integrated device structure while eliminating local step height differences that would compromise metallization quality in both memory and logic regions.
3Reliability
If non-uniform surface is present before metallization, then device functionality is maintained, but surface damage and residues at corners occur during metallization process
Solution Approach 1:
The patent performs preliminary planarization by filling recesses with fill material before interlayer dielectric deposition and metallization processes. This preliminary action creates a uniform surface that eliminates the conditions for surface damage and corner residues during subsequent metallization, while preserving device functionality through maintained structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively planarizes the semiconductor surface, reducing step height differences to negligible levels, preventing defects like shorting and performance degradation, and ensuring a uniform thickness of the interlayer dielectric layer across memory and logic regions, enhancing the production yield and reliability of EDRAM devices.
Implementation Method 1
a bottom anti-reflective coating layer conformal to the photoresist and the semiconductor substrate is formed
Implementation Method 2
A planarization process is performed to the semiconductor substrate
Data Source
AI summary
A method of planarizing a semiconductor device includes forming a first region and a second region on a semiconductor substrate. The first region has a larger thickness than a thickness of the second region. An interlayer dielectric layer is conformally deposited on the first region and the second region. A photoresist is formed on the second region. A bottom anti-reflective coating layer is formed on the photoresist, first region and second region. A planarization process is performed to the semiconductor substrate. The planarization process to the first region and the second region includes removing portions of the interlayer dielectric layer, the photoresist and the BARC layer.