Barrel-Incrementer Round-Robin Scheduler for Multi-Port Switch Priority Management
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Solution Overview
Problem
Multi-port switches face challenges in implementing a customizable transaction scheduling policy that balances fairness and quality-of-service among competing ports, particularly when dealing with varying priority levels and dynamic changes, while avoiding complexity and potential performance degradation.
Innovation Solution
A round-robin transaction scheduler using a barrel incrementer and combinational logic to select transaction queues, allowing for dynamic prioritization and efficient bandwidth allocation across multiple priority levels, with a scalable architecture that maintains low latency and minimal size growth with the number of transaction queues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a customizable transaction scheduling policy is implemented in multi-port switches, then quality of service and fairness among competing ports are improved, but device complexity increases
Solution Approach 1:
The scheduling policy circuitry is segmented into multiple independent round-robin circuits, each handling a specific priority level. This segmentation allows customization at each level without affecting others, improving adaptability while managing complexity through modular design.
Solution Approach 2:
The system implements dynamic priority assignment where transaction queues can be assigned to different priority levels based on quality of service requirements. This dynamic configurability enhances adaptability while the underlying round-robin mechanism maintains consistent, manageable complexity.
2Adaptability or versatility
If conventional round-robin circuitry is used to accommodate variable subsets of requestors, then adaptability is improved, but device complexity increases significantly
Solution Approach 1:
The round-robin circuitry is segmented into multiple independent circuits, each handling a fixed set of requestors at a specific priority level. This segmentation reduces the complexity of each individual circuit while maintaining overall adaptability through the combination of multiple simplified circuits.
Solution Approach 2:
Instead of implementing a single complex round-robin circuit that handles all possible requestor subsets, the system implements multiple partial round-robin circuits, each handling a specific subset corresponding to a priority level. This partial action approach reduces individual circuit complexity while achieving the desired adaptability.
3Adaptability or versatility
If multiple priority levels are implemented with independent round-robin circuits, then quality of service differentiation is improved, but device complexity increases
Solution Approach 1:
The system segments the scheduling function into multiple independent round-robin circuits, each dedicated to a specific priority level. This segmentation enables quality of service differentiation while keeping each circuit relatively simple and manageable.
Solution Approach 2:
Each round-robin circuit is designed to be universal in its ability to handle variable subsets of requestors within its priority level. This multi-functionality allows the same circuit design to be replicated across multiple priority levels, reducing overall complexity through design reuse.
Data Source
AI summary
An apparatus selects one of N transaction queues from which to transmit a transaction out a port of a switch. A first input value specifies the last-selected queue. Only one of the N bits of the first value corresponding to the last selected queue is true. A second input value specifies which queue is enabled for selection. Each of the N bits of the second value whose corresponding queue is enabled is false. A barrel incrementer 1-bit left-rotatively increments the second value by the first value to generate a sum. Combinational logic generates a third value specifying which queue is selected next. The third value is a Boolean AND of the sum and an inverted version of the second value. Only one of the N bits of the third value corresponding to the next selected one of the queues is true.


