Barrel-Threaded Processor With Shared Weight Registers for Arithmetic
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Solution Overview
Problem
Conventional processors lack an efficient mechanism for concurrent threads to operate on shared operand values and thread-specific operands, particularly in applications like neural networks where multiple threads require common weights for operations such as convolutions.
Innovation Solution
A processor with a barrel-threaded execution unit and shared weights registers allows concurrent threads to access a common set of weights registers, enabling arithmetic instructions to perform operations using both shared and thread-specific operands, with the shared weights registers being implicit or explicitly specified by the opcode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each thread has its own separate arithmetic operand registers, then thread-specific operations are straightforward, but threads cannot efficiently share common operands like weights
Solution Approach 1:
The patent combines separate thread-specific operand registers with shared weight operand registers into a unified register file structure. Multiple thread contexts can access the same weight registers simultaneously, enabling efficient operand sharing while maintaining thread-specific data in separate registers. This merging resolves the contradiction by allowing both thread-specific operations and shared operand access within a single integrated register file.
Solution Approach 2:
The register file is designed with universal weight registers that can be accessed by any thread context, making the register structure multi-functional. The same physical registers serve both thread-specific purposes (when exclusively accessed) and shared purposes (when accessed by multiple threads). This universality enables the register file to adapt to different operational modes without requiring separate dedicated structures.
2Productivity
If separate register files are used for each thread, then thread context isolation is maintained, but memory bandwidth and access efficiency are reduced
Solution Approach 1:
Multiple thread contexts share a common register file structure rather than each thread having completely separate physical registers. The register file is organized to allow simultaneous access by multiple threads through context switching and selective enabling, reducing the total quantity of storage required while maintaining efficient concurrent execution through logical separation of thread data.
Solution Approach 2:
The register file is segmented into different regions or banks that can be independently accessed by different threads. Thread-specific operands are stored in dedicated segments while shared weight operands are stored in common segments. This segmentation allows parallel access patterns where multiple threads can simultaneously access different segments, improving productivity without requiring proportional increases in total storage capacity.
3Speed
If threads access shared weights sequentially, then register access is simplified, but execution throughput is limited
Solution Approach 1:
The register access control mechanism is made dynamic, allowing the system to switch between different access modes based on the current operational requirements. When threads need to access shared weights, the control logic dynamically enables simultaneous access paths rather than forcing sequential access. This dynamic adaptability increases execution speed while the control complexity is managed through hardware logic that automatically handles the switching based on context state.
Solution Approach 2:
An intermediary control mechanism is introduced between the thread contexts and the shared weight registers. This intermediary layer manages access requests from multiple threads, resolving conflicts and enabling simultaneous access when possible. The mediator handles the complexity of access coordination, allowing threads to access shared weights at high speed without direct threads managing the complexity themselves.
Data Source
AI summary
A processor comprising a barrel-threaded execution unit for executing concurrent threads, and one or more register files comprising a respective set of context registers for each concurrent thread. One of the one or more register files further comprises a set of shared weights registers common to some or all of the concurrent threads. The types of instructions defined in the instruction set of the processor include an arithmetic instruction having operands specifying a source and a destination from amongst a respective set of arithmetic registers of the thread in which the arithmetic instruction is executed. The execution unit is configured so as, in response to the opcode of the arithmetic instruction, to perform an operation comprising multiplying an input from the source by at least one of the weights from at least one of the shared weights registers, and to place a result in the destination.