Barrel Processor Thread Parking for Cache Eviction Latency
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Solution Overview
Problem
Existing barrel processors require threads to traverse the entire pipeline multiple times for multiple data cache operations, leading to inefficiencies and increased latency, particularly in scenarios where cache eviction is needed.
Innovation Solution
Implementing a first-in-first-out (FIFO) queue near the processor's data cache to park threads, allowing them to be reinserted into the pipeline during empty cycles, thereby reducing the need for rescheduling and minimizing latency for cache eviction operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If threads traverse the entire pipeline multiple times for multiple data cache operations, then cache eviction can be performed, but latency increases and efficiency decreases
Solution Approach 1:
The pipeline is segmented into functional stages with a dedicated parking queue inserted between stages. This allows threads to be parked in the queue during empty cycles rather than traversing the entire pipeline multiple times, reducing latency while maintaining cache eviction functionality.
Solution Approach 2:
A parking queue is introduced as an intermediary structure between pipeline stages. This queue acts as a buffer that holds threads during empty cycles, eliminating the need for threads to traverse the complete pipeline repeatedly and thus reducing the time loss associated with multiple traversals.
2Productivity
If threads are frequently rescheduled for multiple cache operations, then cache eviction can be completed, but the scheduler burden increases
Solution Approach 1:
The scheduling function is extracted from the main pipeline execution flow and relocated to the parking queue mechanism. The parking queue handles thread management and scheduling decisions independently, reducing the scheduler's burden by offloading these responsibilities to the queue structure.
Solution Approach 2:
The parking queue operates autonomously to manage thread parking and resumption during empty cycles. It self-regulates thread placement and retrieval without requiring continuous scheduler intervention, thereby simplifying the overall scheduling complexity while ensuring cache operation completion.
Data Source
AI summary
Devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. A barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.