Barrel Processor Thread Scheduling for Memory Contention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-threaded barrel processors, memory contention between threads accessing a single memory device can lead to slowdowns and stalls in the compute pipeline, resulting in wasted time and energy due to unnecessary cycles spent rescheduling operations.
Innovation Solution
Implementing a thread scheduling control mechanism that organizes threads into separate groups, each with its own memory device, and alternates between groups for read and write access to eliminate memory contention, allowing threads to progress more efficiently through the pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single memory device is shared among multiple threads, then device complexity is reduced, but memory contention occurs causing pipeline slowdowns and stalls
Solution Approach 1:
The patent divides threads into separate groups (e.g., even and odd thread groups) that access the memory device at different times. This temporal segmentation allows multiple threads to share a single memory device without contention, as each group is granted exclusive access during its designated time slots, eliminating pipeline stalls while avoiding the complexity of multi-port memory devices.
2Device complexity
If memory access is serialized to avoid contention, then memory device complexity is reduced, but loss of time increases due to rescheduling cycles
Solution Approach 1:
The patent implements periodic alternating access patterns where different thread groups are granted memory access in regular time slots (e.g., even threads at cycle 0, odd threads at cycle 1). This periodic scheduling eliminates the need for complex rescheduling operations and associated time losses, as the access pattern is predetermined and systematic, allowing efficient memory utilization without pipeline disruptions.
3Productivity
If more memory ports are added to handle concurrent access, then productivity increases, but device complexity and cost increase
Solution Approach 1:
Instead of adding multiple memory ports to handle concurrent access, the patent segments the thread access timeline into distinct time slots. This temporal segmentation allows a single memory port to serve multiple threads sequentially without contention, achieving the same productivity benefits as multi-port memory would provide, but with significantly reduced device complexity and cost.
Data Source
AI summary
Devices and techniques for sharing thread memory in a barrel processor via scheduling are described herein. An apparatus includes a barrel processor, which includes thread scheduling circuitry, where the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: place a thread to be scheduled in one of two groups: a first group and a second group, wherein the first group is associated with a first processor storage device, and the second group is associated with a second processor storage device; and schedule a current thread to place into a pipeline for the barrel processor, the scheduling performed by alternating between threads in the first group and threads in the second group.