Barrel Shifter for Data Alignment and Sign Extension

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Solution Overview

Problem

Existing data processing systems require separate load-permute data paths to align and store data from memory into a register file, which is inefficient and complex, especially for handling shift operations on large data values.

Innovation Solution

A data processing apparatus with first and second shift circuitry that allows for bit-level and byte-level shifting, along with masking and permutation, to align and store data within a register file without the need for a separate load-permute data path, using control signals to manage the shifting and masking operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate load-permute data paths are used to align and store data from memory into the register file, then data alignment functionality is provided, but the device complexity increases and efficiency decreases

Engineering Contradiction:
Improvedata alignment functionalityVSAvoidseparate load-permute data path
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The barrel shifter is designed to perform multiple functions: it can shift data values by specified bit positions, align data from memory loads to the least significant byte position, and provide sign extension. By making the barrel shifter universal and capable of handling both general-purpose shifting and load data alignment tasks, the patent eliminates the need for separate dedicated load-permute data paths, thereby reducing device complexity while maintaining full data alignment functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If a barrel shifter is implemented as a series of multiplexer stages to shift large data values by large shift amounts, then shifting capability is provided, but the quantity of components increases

Engineering Contradiction:
Improveshifting capabilityVSAvoidnumber of multiplexers
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The barrel shifter is segmented into multiple stages, where each stage consists of multiplexers that shift data by a specific bit position. For a 32-bit data value, multiple stages work in parallel to achieve the total required shift amount. This segmentation allows the system to handle large shift amounts efficiently by breaking down the complex shifting operation into manageable stages, each contributing a portion of the total shift.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If switching circuitry is added to align load data to the least significant byte position, then data alignment is achieved, but the device complexity increases

Engineering Contradiction:
Improvedata alignmentVSAvoidswitching circuitry
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The barrel shifter is designed to perform multiple functions: it can shift data values by specified bit positions, align data from memory loads to the least significant byte position, and provide sign extension. By making the barrel shifter universal and capable of handling both general-purpose shifting and load data alignment tasks, the patent eliminates the need for separate dedicated load-permute data paths, thereby reducing device complexity while maintaining full data alignment functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8291002B2Barrel shifter
Publication Date: 2012.10.16 ARM LTD
  • US8291002B2 patent drawing
  • US8291002B2 patent drawing
  • US8291002B2 patent drawing

AI summary

A data processing apparatus includes a register file having a set of registers for storing data values for processing by processing circuitry. The apparatus has first shift circuitry arranged to receive a data value from the register and selection circuitry is responsive to a second control signal to select between the first shifted data value and a load data value received from a memory. Second shift circuitry is arranged to receive the data value selected by the selection circuitry and is responsive to a third control signal indicating a second shift amount S2 of a x (n+1) bit positions to generate a second shifted data value by shifting bit values within the received selected data value by the second shift amount S2, where a is zero or an integer. The second shift circuitry is then operable to output the second shifted data value to the register file.