Barrier Layered CUF for Multi-Chip Package Underfill Flow

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Solution Overview

Problem

In multi-chip packaging, the capillary underfill material fails to flow under the die and around the interconnects due to surface energy created by conductive pillars, leading to reliability issues and requiring increased spacing to prevent segregation, which increases the module's form factor.

Innovation Solution

A barrier layer is set into the array of conductive pillars to confine and direct the capillary underfill material, allowing it to flow under the die and around the interconnects, with the option of a sacrificial barrier layer that can be removed after curing to meet reliability standards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the spacing between conductive pillars and the first die is increased to create a larger keep out zone, then the underfill material can flow properly under the die, but the form factor of the multi-die module increases

Engineering Contradiction:
Improveunderfill dispensing reliabilityVSAvoidmodule form factor
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

A barrier layer is introduced as an intermediary element between the conductive pillars and the underfill material. This barrier layer has controlled wettability that prevents the underfill from being absorbed by the conductive pillars while allowing it to flow properly under the die, thereby eliminating the need for increased spacing and maintaining a compact module form factor

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The wettability parameters of the barrier layer are specifically controlled to create a wettability gradient that directs underfill flow. By adjusting the surface energy characteristics of the barrier layer relative to the conductive pillars and die, the underfill material is guided to flow under the die while preventing segregation to the conductive pillars, resolving the contradiction between reliable dispensing and compact dimensions

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the spacing between conductive pillars and the first die is increased to prevent underfill segregation, then underfill material can be properly contained, but the manufacturing precision requirements increase

Engineering Contradiction:
Improveunderfill material containmentVSAvoidspacing control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The barrier layer serves as a controllable intermediary that provides a defined interface between the conductive pillars and underfill material. This barrier layer can be precisely controlled during manufacturing through deposition processes, providing a reliable containment mechanism that does not depend on variable spacing between components, thereby reducing manufacturing precision requirements

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The barrier layer is formed on the conductive pillars before underfill dispensing, establishing predetermined wettability characteristics that control underfill flow behavior. This preliminary action ensures that the underfill material will be contained and directed properly during the dispensing process without requiring precise control of spacing parameters

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The barrier layer ensures proper dispensing of the underfill material under the die, enhancing the reliability of the electronic package by preventing segregation and maintaining a compact module form factor.

Implementation Method 1

capillary underfill (CUF) material

Methodology Applied
Scientific EffectCapillary action: Capillary Action

Data Source

PatentUS20240153837A1Barrier enabled CUF and mold process for multi-chip packaging
Publication Date: 2024.05.09 INTEL CORP
  • US20240153837A1 patent drawing
  • US20240153837A1 patent drawing
  • US20240153837A1 patent drawing

AI summary

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die, and an array of pillars adjacent to the die. In an embodiment, the electronic package further comprises an underfill under the die, where an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, and where the edge of the underfill has a height that is less than a maximum height of the underfill.