Barrier-Free Interconnect Air Gaps for Lower RC Delay
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Solution Overview
Problem
The semiconductor industry faces challenges in forming high-quality interconnects due to increased parasitic resistance and capacitance caused by diffusion barrier layers and the need for costly chemical mechanical polishing (CMP) processes as IC dimensions scale down.
Innovation Solution
The implementation of barrier-free interconnect layers involves selectively depositing a barrier layer on the sidewalls of trenches in the metal interconnect layer, followed by rapid atomic layer deposition (ALD) of the inter-metal dielectric (IMD) layer using a catalyst layer, and subsequently removing the barrier layer to create air gaps, thereby reducing parasitic capacitance and eliminating the need for CMP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diffusion barrier layers are used in metal interconnect layers, then metal diffusion is prevented, but parasitic resistance and capacitance increase
Solution Approach 1:
The patent removes the diffusion barrier layer from the metal interconnect structure entirely, replacing it with an air gap formed by selectively depositing and then removing the barrier material. This extraction eliminates the source of high parasitic capacitance while maintaining diffusion prevention through the air gap configuration
Solution Approach 2:
The patent changes the dielectric parameter from high-k barrier layer material to air (k=1.0) in the interconnect structure. This parameter change dramatically reduces parasitic capacitance while the air gap configuration maintains the necessary diffusion barrier function
2Manufacturing precision
If chemical mechanical polishing (CMP) is used for inter-metal dielectric layers, then planarization is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent employs self-aligned deposition processes where the barrier layer is selectively deposited only on metal surfaces, and the air gap formation is self-aligned to the metal structures. This self-service approach eliminates the need for separate CMP planarization steps while maintaining manufacturing precision
Solution Approach 2:
The patent replaces the mechanical CMP process with a chemical vapor deposition-based air gap formation process. This substitution eliminates mechanical polishing while achieving the necessary planarization and surface preparation through controlled chemical deposition and selective removal
3Manufacturing precision
If conventional ALD deposition is used for inter-metal dielectric layer, then good coverage is achieved, but deposition time is excessive
Solution Approach 1:
The patent applies a preliminary catalyst layer deposition step before the main ALD IMD layer deposition. This preliminary action activates the surface and enables rapid subsequent deposition, reducing overall deposition time by around 90% while maintaining good coverage quality
Solution Approach 2:
The patent changes the deposition rate parameter by introducing a catalyst layer that enables faster ALD kinetics. This parameter change accelerates the IMD layer deposition while the catalyst layer ensures uniform coverage and nucleation across the substrate surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces parasitic capacitance and associated RC delay, eliminates the need for costly CMP processes, and enhances processing throughput by reducing the ALD IMD layer deposition time by around 90%. Additionally, air gaps replace high dielectric constant barrier layers, further reducing parasitic capacitance.
Implementation Method 1
rapid atomic layer deposition (ALD) of the inter-metal dielectric (IMD) layer using a catalyst layer
Implementation Method 2
significantly reduces parasitic capacitance and associated RC delay
Data Source
AI summary
A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.