Barrier-Free Interconnect Interface for Integrated Chips
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Solution Overview
Problem
As integrated chip interconnects shrink, increased capacitance and resistance lead to performance bottlenecks due to the use of barrier layers that raise resistance and cause electrical shorting, despite their inability to prevent metal atom diffusion into the ILD structure.
Innovation Solution
An integrated chip design with interconnects where a barrier layer laterally surrounds the second interconnect, preventing diffusion into the ILD structure without vertically separating it from the first interconnect, thus reducing resistance and maintaining low electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is used to surround interconnects, then metal atom diffusion into the ILD structure is prevented, but interconnect resistance increases significantly
Solution Approach 1:
The barrier layer is segmented into two distinct portions: a lateral barrier portion that extends along the sidewalls to prevent metal atom diffusion into the ILD structure, and a removed vertical barrier portion at the interface region that would otherwise increase resistance. This segmentation allows the barrier layer to provide diffusion protection while eliminating the resistance-increasing vertical section at the critical interconnect interface.
Solution Approach 2:
The barrier layer structure is designed with different properties in different regions: the lateral portions maintain barrier properties to prevent diffusion, while the vertical portion at the interface is removed to create a low-resistance path. This local quality variation optimizes both diffusion prevention and electrical conductivity in their respective regions.
2Productivity
If interconnects are shrunk to maintain scaling, then device density increases, but capacitance and resistance increase causing performance bottlenecks
Solution Approach 1:
The harmful vertical barrier portion is extracted and removed from the interface region, leaving only the necessary lateral barrier portions. This extraction eliminates the source of increased resistance while maintaining the diffusion protection function, thereby reducing the harmful electrical effects associated with scaled-down interconnects.
3Reliability
If a continuous barrier layer is used to prevent diffusion, then reliability is improved, but electrical shorting and resistance increase occur
Solution Approach 1:
The continuous barrier layer is segmented by removing the vertical portion at the interface, creating a discontinuous structure that allows electrical contact while maintaining lateral diffusion protection. This segmentation prevents electrical shorting and reduces resistance while preserving the essential diffusion barrier function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces interconnect resistance by approximately 20% and improves integrated chip performance, such as increasing ring oscillator speed by 1.5% or more, by eliminating the barrier layer's resistance impact.
Implementation Method 1
a barrier layer laterally surrounds the second interconnect, preventing diffusion into the ILD structure
Implementation Method 2
reduces interconnect resistance by approximately 20% and improves integrated chip performance
Data Source
AI summary
The present disclosure relates an integrated chip. The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate. A barrier layer is disposed along sidewalls of the ILD structure. The barrier layer has sidewalls defining an opening over the first interconnect. A second interconnect is disposed on the barrier layer. The second interconnect extends through the opening in the barrier layer and to the first interconnect.