Barrier-Free Via Bottom Interconnects for Lower Contact Resistance
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes is increased by the shrinking interconnect dimensions, which require low resistance and high reliability, particularly in forming interconnects with minimal barrier layers on the bottom surface of vias.
Innovation Solution
The formation of interconnect structures without a barrier layer on the bottom surface of vias is achieved through selective deposition and removal processes, utilizing methods like CVD, PECVD, ALD, and SAM to minimize barrier layer thickness and enhance conductive material proportion, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is formed on the bottom surface of via to prevent diffusion, then reliability is improved, but contact resistance increases and conductivity decreases
Solution Approach 1:
The patent removes the barrier layer from the bottom surface of the via, extracting only the necessary barrier function from the problematic location. The barrier layer is retained on the via sidewalls and trench surfaces where diffusion prevention is needed, but eliminated from the via bottom where it causes high contact resistance.
Solution Approach 2:
The patent applies different barrier layer configurations to different locations: full barrier coverage on trench surfaces and via sidewalls for diffusion prevention, but no barrier on the via bottom surface for optimal electrical contact. This localized differentiation resolves the contradiction between reliability and conductivity.
2Productivity
If interconnect dimensions are shrunk to increase device density, then productivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent simplifies the manufacturing process by removing the barrier layer formation step from the via bottom surface, reducing process complexity. This extraction of the unnecessary barrier layer function allows for simpler deposition processes while maintaining diffusion prevention through selective barrier placement on sidewalls and trenches.
Solution Approach 2:
The patent changes the barrier layer configuration parameter from uniform coverage to selective coverage, with thickness and presence varying by location. This parameter differentiation simplifies the overall process by eliminating redundant barrier material deposition on via bottoms while maintaining protective barriers where needed.
3Manufacturing precision
If barrier layer thickness is reduced to decrease resistance, then electrical conductivity is improved, but diffusion prevention capability deteriorates
Solution Approach 1:
The patent segments the barrier layer function into two distinct locations: diffusion prevention is handled by barriers on trench surfaces and via sidewalls, while electrical contact is optimized by removing barriers from the via bottom surface. This segmentation allows each function to be optimized independently without compromise.
Solution Approach 2:
The via sidewall barrier layer acts as an intermediary that provides diffusion prevention without interfering with electrical contact. By placing the barrier on the sidewall rather than the bottom surface, it mediates between the conflicting requirements of diffusion blocking and low contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in interconnect structures with lower resistance and improved reliability by minimizing the barrier layer thickness and eliminating interfaces between conductors, enhancing the conductivity and stability of semiconductor devices.
Implementation Method 1
utilizing methods like CVD, PECVD, ALD, and SAM to minimize barrier layer thickness
Implementation Method 2
utilizing methods like CVD, PECVD, ALD, and SAM to minimize barrier layer thickness
Implementation Method 3
utilizing methods like CVD, PECVD, ALD, and SAM to minimize barrier layer thickness
Data Source
AI summary
Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.