3D Memory Device With Barrier Layer Ferroelectric Isolation
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Solution Overview
Problem
Conventional memory devices with perovskite structure ferroelectric materials require thick layers (>200 nm) for ferroelectric characteristics, making it difficult to miniaturize ferroelectric field effect transistors and affecting data writing, reading, and storage as the ferroelectric characteristics can be compromised during fabrication and usage.
Innovation Solution
A three-dimensional memory device with vertically stacked memory cells, featuring a composite structure of gate conductive and ferroelectric layers isolated by a barrier layer, which prevents diffusion of atoms from the gate insulating layer, maintaining ferroelectric characteristics and enabling higher data storage capacity per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick ferroelectric material layer (>200 nm) with perovskite structure is used to ensure ferroelectric characteristics, then the ferroelectric characteristic is maintained, but the device size cannot be reduced and manufacturing complexity increases
Solution Approach 1:
The patent changes the material parameter from perovskite structure to non-perovskite ferroelectric material, which allows achieving ferroelectric characteristics at much thinner layer thicknesses (below 200 nm), thereby reducing device size while maintaining reliability
Solution Approach 2:
The patent introduces a barrier layer as an intermediary between the ferroelectric layer and gate insulating layer to prevent harmful diffusion, enabling the use of thin non-perovskite ferroelectric materials without compromising their ferroelectric characteristics during fabrication and operation
2Reliability
If a thick ferroelectric material layer is used to maintain ferroelectric characteristics, then data storage capacity is limited, but manufacturing process complexity increases
Solution Approach 1:
By changing from perovskite to non-perovskite ferroelectric material, the required layer thickness parameter is dramatically reduced, simplifying the manufacturing process as thinner layers are easier to deposit with better uniformity and fewer defects
Solution Approach 2:
The barrier layer serves as a protective intermediary that prevents contamination during manufacturing, ensuring that thin ferroelectric layers maintain their characteristics throughout the fabrication process without requiring overly complex manufacturing controls
3Ease of manufacture
If the ferroelectric layer is in direct contact with the gate insulating layer, then manufacturing is simpler, but atoms diffuse between layers degrading ferroelectric characteristics
Solution Approach 1:
The patent introduces a barrier layer as an intermediary between the ferroelectric layer and gate insulating layer. This barrier layer prevents atomic diffusion while adding minimal structural complexity, as it can be integrated into existing fabrication processes as an additional thin film layer
Solution Approach 2:
The patent creates a composite structure consisting of multiple functional layers (ferroelectric layer, barrier layer, gate insulating layer) where each layer serves a specific purpose. This composite approach maintains manufacturing feasibility while preventing harmful interactions between materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for a compact memory device design with enhanced data storage capacity and retention by isolating the ferroelectric layer from the gate insulating layer, preventing diffusion-induced characteristic degradation and enabling efficient data processing.
Implementation Method 1
Each of the ferroelectric layers and the corresponding one of the gate insulating layers are insulated from each other by the corresponding one of the barrier layers
Data Source
AI summary
A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom source lines extending in a first horizontal direction, a stacked structure disposed on the bottom source lines, a plurality of bit lines extending in a second horizontal direction, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of composite structures spaced apart from one another and respectively located at different levels. The composite structures each include a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer. Each of the pillar structures connected between the corresponding bit line and the corresponding bottom source line includes a barrier layer, a gate insulating layer, and a channel layer. The ferroelectric layer of each composite structure is insulated from the gate insulating layer of the pillar structure by the barrier layer.