Array Substrate Barrier Layer Groove for Etching Control
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Solution Overview
Problem
In the manufacturing of thin film transistors, over-etching during the etching process can lead to incomplete etching or damage of the insulating layer under the barrier layer, causing it to be too thin and potentially resulting in electric leakage, especially in display panels with large sizes and high resolution requirements.
Innovation Solution
The solution involves creating a thin film transistor structure with a connecting groove in the barrier layer that connects the source and drain electrodes, allowing for a smaller etching area and preventing over-etching, which includes a closed-loop or open-loop through-groove structure with specific dimensions to ensure uniform etching and protect the insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a small area thin film transistor structure is used, then the aperture ratio is improved, but the etching uniformity deteriorates causing over-etching or incomplete etching
Solution Approach 1:
The patent divides the barrier layer into two distinct regions: a first barrier layer region covering the active area and a second barrier layer region covering the source/drain electrode areas. This segmentation allows different etching processes to be applied to different regions, with the second region having openings that prevent over-etching while maintaining the small TFT area for improved aperture ratio.
Solution Approach 2:
The patent performs preliminary formation of the second barrier layer region with openings before the main etching process. This preliminary action creates a protective structure that prevents over-etching of the insulating layer during subsequent etching steps, ensuring etching uniformity while maintaining the small TFT footprint.
2Reliability
If over-etching occurs during the etching process, then the barrier layer is completely etched, but the insulating layer underneath is damaged causing it to be too thin and potentially leading to electric leakage
Solution Approach 1:
The patent creates a beforehand cushioning structure by forming the second barrier layer region with openings that extend through the barrier layer. This structure acts as a cushion or buffer that stops the etching process before it can reach and damage the insulating layer, preventing over-etching while ensuring complete removal of the barrier layer where needed.
Solution Approach 2:
The second barrier layer region with openings serves as an intermediary structure between the barrier layer and the insulating layer. It mediates the etching process by providing a controlled pathway that allows complete etching of the barrier layer in specific areas while preventing etching penetration into the insulating layer, thus protecting it from damage.
3Manufacturing precision
If the insulating layer becomes too thin due to over-etching, then etching completeness is achieved, but electric leakage occurs reducing display panel reliability
Solution Approach 1:
The second barrier layer region with openings provides beforehand cushioning that prevents etching from penetrating too deeply into the insulating layer. This cushioning structure ensures that while the barrier layer is completely etched where needed, the insulating layer maintains sufficient thickness to prevent electric leakage, thereby preserving display panel reliability.
Data Source
AI summary
The application discloses an array substrate, a manufacturing method of the array substrate and a display panel. It includes a thin film transistor, and the thin film transistor includes a substrate, a Metal 1, an insulating layer, a semiconductor layer, a barrier layer, a Metal 2, a first passivation layer and a pixel electrode; the Metal 2 includes a source electrode and a drain electrode. A connecting groove is arranged on the barrier layer corresponding to the position of the source electrode and the drain electrode, one end of the connecting groove is connected to the source electrode and the semiconductor layer, and the other end is connected to the drain electrode and the semiconductor layer.