Barrier Layer Groove for Semiconductor Memory Wiring
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization, low power consumption, and high performance due to limitations in the fabrication and integration of variable resistance elements in memory circuits, particularly in forming reliable metal wirings and barrier layers that prevent diffusion and resistance increase.
Innovation Solution
The proposed electronic device incorporates a semiconductor memory with a variable resistance element, a top electrode, a barrier layer, and metal wiring, where the barrier layer surrounds the metal wiring and includes a groove structure, using tantalum and copper materials, and an insulating layer with air gaps to improve integration and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional fabrication process is used for metal wirings and barrier layers, then the manufacturing complexity is high, but the fabrication process becomes simplified with the groove structure in the barrier layer
Solution Approach 1:
The barrier layer is segmented into two distinct parts: a first barrier layer portion and a second barrier layer portion separated by a groove. This segmentation allows each portion to be optimized independently - the first portion provides diffusion barrier functionality while the second portion enables direct contact between metal wiring and interlayer dielectric, simplifying the overall fabrication process by eliminating the need for complete barrier layer removal or modification.
Solution Approach 2:
The groove structure extracts or removes a portion of the barrier layer to create a localized opening. This extracted region allows the metal wiring to directly contact the interlayer dielectric layer without requiring the entire barrier layer to be removed or modified, thereby simplifying the fabrication process while maintaining barrier functionality in other regions.
2Reliability
If the barrier layer completely surrounds the metal wiring, then diffusion prevention is effective, but the metal wiring resistance increases
Solution Approach 1:
The barrier layer exhibits local quality variations through its groove structure. In regions where the barrier layer is present (first barrier layer portion), it provides strong diffusion prevention. In the groove region, the barrier layer is absent, allowing direct metal wiring-to-interlayer dielectric contact that reduces resistance. This local differentiation optimizes both diffusion prevention and electrical performance.
Solution Approach 2:
Instead of completely removing the barrier layer surrounding the metal wiring, the invention applies partial action by removing only a specific portion (creating the groove). This partial removal is sufficient to reduce metal wiring resistance while maintaining adequate diffusion barrier coverage in other critical regions, achieving optimal balance between the two competing requirements.
3Reliability
If multiple fabrication steps are used for forming barrier layers and metal wirings, then the integration reliability is high, but the fabrication yield decreases
Solution Approach 1:
The groove structure in the barrier layer merges the functions of barrier formation and metal wiring integration into a single structural feature. The groove itself serves as both the barrier layer modification and the metal wiring formation template, eliminating the need for separate steps to create openings through the barrier layer and reducing the total number of fabrication steps while maintaining integration reliability.
Solution Approach 2:
The groove structure in the barrier layer is formed in advance before metal wiring deposition. This preliminary action creates a pre-defined pathway and contact region that guides subsequent metal wiring formation, ensuring proper integration and reducing the need for additional alignment or modification steps, thereby improving fabrication yield.
Data Source
AI summary
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a variable resistance element formed over the substrate; a top electrode formed over the variable resistance element; a barrier layer formed over the top electrode and including a groove; an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer; and a metal wiring including a portion formed in the groove of the barrier layer.