Barrier Layer Height Control in Replacement Gate Trenches
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Solution Overview
Problem
Conventional poly-silicon gates in semiconductor devices face performance issues due to boron penetration and depletion effects as devices scale down, leading to increased equivalent thickness of the gate dielectric layer and reduced gate capacitance, necessitating the use of work function metals in metal gate stack structures, which encounter manufacturing challenges as critical dimensions shrink.
Innovation Solution
The method involves performing different pull-down processes on barrier layers in trenches with varying trench densities to reduce height variations and improve electrical properties, using masks to control the etching of barrier layers in regions with distinct trench densities, thereby ensuring consistent barrier layer heights across different trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional poly-silicon gates are used in scaled-down semiconductor devices, then manufacturing process is simple, but performance deteriorates due to boron penetration and depletion effects
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional poly-silicon to metal materials with different work functions. By selecting specific metals (tantalum, titanium, tungsten, molybdenum, niobium, or their nitrides/oxides) with work functions between 3.5-5.0 eV, the gate can maintain effective control over the channel even with high-k dielectric layers, eliminating boron penetration and depletion effects while improving device performance in scaled-down technologies
Solution Approach 2:
The patent creates a composite gate stack structure combining metal gate electrodes with high-k gate dielectric layers. This composite structure integrates the advantages of both materials: the metal provides appropriate work function for effective gate control, while the high-k dielectric (with κ≥5) enables thinner equivalent oxide thickness without increasing physical thickness, thereby improving scaling performance while maintaining manufacturability
2Reliability
If work function metals are used to replace poly-silicon gates, then gate performance is improved, but manufacturing complexity increases due to replacement gate process requirements
Solution Approach 1:
The patent segments the gate structure formation into distinct stages: first forming a dummy gate, then forming spacers, removing the dummy gate to create trenches, and finally filling with metal gate electrode and high-k dielectric layer. This segmentation allows each step to be optimized independently and enables the use of standard semiconductor manufacturing processes for each stage, reducing overall process complexity despite the advanced structure
Solution Approach 2:
The patent performs preliminary actions by first forming the dummy gate structure using conventional processes, then using it as a template for spacer formation. This preliminary structure guides subsequent steps and ensures proper alignment and dimensions for the final metal gate, simplifying the overall manufacturing process by providing a roadmap for subsequent fabrication steps
3Length of moving object
If metal gate stack structures are formed with smaller critical dimensions, then device scaling is achieved, but manufacturing yield decreases due to serious manufacturing problems
Solution Approach 1:
The patent changes the material parameters of both the gate electrode (to metals with work functions 3.5-5.0 eV) and gate dielectric (to high-k materials with κ≥5) to enable effective gate control at smaller critical dimensions. This parameter change allows the gate to maintain sufficient electrostatic control over the channel even when scaled down, enabling continued device scaling without proportionally decreasing manufacturing yield
Solution Approach 2:
The patent achieves equipotentiality in the gate structure by carefully selecting metal materials with work functions in the 3.5-5.0 eV range, which creates an optimal potential distribution between the gate electrode and the high-k dielectric layer. This equipotential design ensures uniform electric field distribution across the gate stack, improving manufacturing consistency and yield at smaller critical dimensions
4Adaptability or versatility
If different trench densities exist in different regions, then device functionality is achieved, but barrier layer height variation increases due to etching loading effects
Solution Approach 1:
The patent applies local quality by performing different pull-down processes on barrier layers in regions with different trench densities. Regions with high trench density receive one etching treatment while regions with low trench density receive a different treatment, ensuring that each region's barrier layer achieves the target height despite varying etching loading effects. This localized process adjustment maintains manufacturing precision across the entire wafer
Solution Approach 2:
The patent changes the etching process parameters (such as etchant composition, temperature, pressure, or power) when performing pull-down processes on barrier layers in different trench density regions. By adjusting these parameters locally, the etching rate is optimized for each region's specific conditions, compensating for etching loading effects and achieving uniform barrier layer heights across regions with different trench densities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the height variation range of the barrier layer, enhancing the electrical properties and manufacturing yield of semiconductor devices by addressing the challenges associated with varying trench densities and etching loading effects.
Implementation Method 1
A first pull-down process is performed to the barrier layer in the trenches formed on the second region. The barrier layer in the trenches formed on the first region is covered by a first mask during the first pull-down process. A second pull-down process is performed to the barrier layer in the trenches formed on the first region.
Data Source
AI summary
A manufacturing method of a semiconductor device includes the following steps. Trenches are formed on a substrate, and the trenches are formed on a first region and a second region defined on the substrate. A barrier layer is formed conformally in the trenches. A first pull-down process is performed to the barrier layer on the second region. The barrier layer on the first region is covered by a first mask during the first pull-down process. A second pull-down process is performed to the barrier layer on the first region. The barrier layer on the second region is covered by a second mask during the second pull-down process. A proportion of an area of the trenches on the first region to an area of the first region is different from a proportion of an area of the trenches on the second region to an area of the second region.