Multi-VT Control via Barrier Layer Thickness Modulation
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Solution Overview
Problem
Traditional methods for achieving multi-threshold voltage (multi-VT) in semiconductor devices, especially for FINFETs with fin widths smaller than 10 nm, face challenges due to reduced doping impact and lower mobility caused by high channel doping, necessitating alternative solutions.
Innovation Solution
The method involves a gate-last approach with a replacement metal gate process, using a series of barrier layers with varying thicknesses and compositions, such as TiN and TaN, to adjust the effective work function of gate stacks, allowing for independent control of threshold voltages in CMOS devices by selectively removing portions of these layers to create different gate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional doping methods are used to achieve multi-VT in FINFETs, then threshold voltage can be adjusted, but mobility decreases due to scattering and dopant fluctuations cause worse mismatch
Solution Approach 1:
The patent changes the physical parameter approach from chemical doping to physical barrier layer thickness modulation. By varying the thickness of barrier layers (e.g., TiN, TaN) in the gate stack, the effective work function is tuned, thereby controlling threshold voltage without introducing dopant-related scattering and fluctuations that degrade mobility and increase mismatch.
Solution Approach 2:
The patent employs composite gate stack structures combining multiple materials with different properties: high-k dielectric layers (e.g., HfO2, Al2O3) for gate insulation, metal layers (e.g., TiN, TaN, W, Pt) for work function tuning, and optional intermediate layers. This composite structure enables precise threshold voltage control through material composition and layer thickness optimization without the adverse effects of channel doping.
2Manufacturing precision
If high channel doping levels are used to achieve multi-VT, then threshold voltage can be adjusted, but mobility is reduced due to scattering
Solution Approach 1:
The patent transitions from changing carrier concentration via doping to changing the gate electrode's effective work function via barrier layer thickness. This parameter change enables threshold voltage adjustment while preserving high carrier mobility in the channel, as no dopants are introduced that would cause scattering.
Solution Approach 2:
The patent replaces the chemical mechanism (doping) with a physical/structural mechanism (barrier layer thickness control). The threshold voltage is controlled by the physical dimension (thickness) of the barrier layer rather than by chemical composition (dopant concentration), thereby avoiding the scattering effects that reduce mobility.
3Adaptability or versatility
If multiple barrier layers with different thicknesses are deposited, then effective work function can be tuned for different gate regions, but process complexity increases
Solution Approach 1:
The patent segments the gate stack into distinct functional layers: high-k dielectric layer, barrier layer(s), and metal layer(s). Each segment can be independently optimized and processed. The barrier layer is further segmented into multiple depositable layers that can be selectively removed or retained to create different thicknesses in different gate regions, enabling work function tuning without overwhelming process complexity.
Solution Approach 2:
The patent performs preliminary deposition of multiple barrier layers with uniform thickness across all gate regions before selective removal. This preliminary action establishes a controlled foundation that simplifies subsequent selective thinning processes. By pre-depositing the full complement of barrier layers uniformly, the process ensures consistent starting conditions that facilitate precise local modifications to achieve different effective work functions.
Data Source
AI summary
The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.