Semiconductor Package Redistribution Layers With Barrier Patterns
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high integration and reliability due to limitations in the design and structure of redistribution substrates, which affect the electrical connectivity and durability of semiconductor chips.
Innovation Solution
The semiconductor package incorporates a redistribution substrate with vertically stacked first and second redistribution layers, each comprising dielectric layers and metal patterns with specific barrier patterns, and metal pillars to enhance electrical connectivity and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single redistribution layer is used in the redistribution substrate, then the device complexity is reduced, but the integration density and electrical connectivity are insufficient
Solution Approach 1:
The patent transitions from a single-plane redistribution structure to a multi-layer vertical stacked structure. The first and second redistribution layers are positioned at different heights (different z-dimension) within the substrate, enabling three-dimensional electrical connectivity. This dimensional expansion allows multiple chip pads to be connected through vertical vias without increasing the planar footprint, thereby increasing integration density while managing complexity through systematic layering
Solution Approach 2:
The redistribution substrate is segmented into multiple functional layers: a first redistribution layer for initial electrical connections, a second redistribution layer for additional connections, and intermediate dielectric layers for isolation. This segmentation allows each layer to serve specific connectivity functions, enabling high integration density through modular organization of electrical pathways
2Reliability
If barrier patterns are added between metal patterns and dielectric layers, then the reliability is improved, but the manufacturing complexity increases
Solution Approach 1:
Barrier patterns are introduced as intermediary layers between the metal redistribution patterns and the dielectric layers. These barrier patterns prevent direct contact between metal and dielectric materials, eliminating harmful electrochemical reactions and improving long-term reliability. The barrier patterns are integrated into the existing layer structure without requiring fundamental design changes, thus managing complexity while enhancing reliability
3Reliability
If vertically stacked redistribution layers are implemented, then the electrical connectivity is enhanced, but the manufacturing precision requirements increase
Solution Approach 1:
Dielectric layers are formed and planarized before the metal redistribution patterns are deposited. This preliminary formation of the dielectric matrix with pre-defined via locations establishes a stable foundation for subsequent metal layer deposition. The preliminary structuring of dielectric layers with embedded via holes ensures precise alignment of metal patterns across multiple layers, reducing manufacturing precision requirements while achieving enhanced electrical connectivity
Data Source
AI summary
A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.