Barrier-Redundancy Interconnects Preventing Electromigration Open Circuits
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Solution Overview
Problem
Existing semiconductor interconnect structures face sudden open circuit failures due to electromigration, particularly in wide lines where void accumulation increases electrical resistivity and can lead to circuit failure, with no adequate solution in prior art to address this issue effectively.
Innovation Solution
Incorporating a barrier-redundancy feature with an electrical conductive material between the diffusion barriers of conductive lines and vias, creating an electrical path to prevent sudden open circuits, and a method of fabricating this structure by selectively introducing the conductive material between the diffusion barriers within preselected locations of the interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional interconnect structure is used, then the signal transmission speed is improved by using copper and low-k dielectric materials, but the reliability deteriorates due to electromigration failure and void accumulation causing sudden open circuits
Solution Approach 1:
The patent applies beforehand cushioning by creating a barrier-redundancy feature that forms an alternative electrical path before electromigration failure occurs. The conductive material is deposited between diffusion barriers in advance, so that when void accumulation or EM damage occurs in the primary interconnect path, the redundant barrier provides a pre-positioned alternative route, cushioning against sudden open circuit failure and maintaining circuit reliability while preserving the high-speed copper interconnect structure.
Solution Approach 2:
The patent uses an intermediary approach by introducing a conductive material as a mediator between the diffusion barriers. This intermediary conductive path acts as a backup communication route that mediates between the unreliable primary copper interconnect and the diffusion barriers, ensuring continuous electrical connection even when the primary path fails due to electromigration or void accumulation.
2Manufacturing precision
If the contact via size is smaller than the underlying metal line, then the manufacturing precision is improved, but the reliability deteriorates because the barrier-redundancy feature cannot be reached through regular process
Solution Approach 1:
The patent applies another dimension by changing the spatial approach from top-down via filling to sidewall deposition. Instead of trying to reach the barrier-redundancy feature through the via opening (which fails when via is smaller than the metal line), the conductive material is deposited on the sidewalls of the via and metal line structures. This sidewall dimension provides access to the barrier interface without requiring the via to be larger than the metal line, thus maintaining manufacturing precision while achieving reliability.
3Reliability
If the barrier-redundancy feature is added to all interconnect structures, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent applies local quality by making the barrier-redundancy feature selective rather than universal. The conductive material is deposited only in specific locations where EM failure is most likely to occur, such as wide lines and critical via regions. This localized approach provides reliability enhancement exactly where needed, while avoiding unnecessary complexity in regions where the standard interconnect structure is sufficient, thus balancing reliability improvement with device complexity management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The barrier-redundancy feature effectively avoids sudden open circuits by providing an electrical path, allowing sufficient time for chip replacement or system adjustment after electromigration failure detection, thereby enhancing the reliability of semiconductor devices.
Implementation Method 1
an electrical conductive material located between, and in contact with, said conductive line diffusion barrier and said via diffusion barrier thereby creating an electrical path between the via diffusion barrier along the sidewalls of the conductively filled via and the conductive line diffusion barrier along the sidewalls of the conductive line
Implementation Method 2
said conductive line having sidewalls that are lined with a conductive line diffusion barrier
Data Source
AI summary
An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect structure including in a wide line region, a thin line region or any combination thereof. The barrier-redundancy feature includes an electrical conductive material located between, and in contact with, a conductive line diffusion barrier of a conductive line and a via diffusion barrier of an overlying via. The presence of the inventive barrier-redundancy feature creates an electrical path between the via diffusion barrier along the sidewalls of the via and the conductive line diffusion barrier along the sidewalls of the conductive line. This electrical path generated by the inventive barrier-redundancy feature can avoid a sudden open circuit resulting from EM failure at the bottom of the via. The presence of the inventive barrier-redundancy feature within an interconnect structure provides sufficient time for chip replacement or system operation.