Barrier Synchronization Circuitry for Multi-Unit Data Consistency
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Solution Overview
Problem
Existing systems for processing units face challenges in coordinating barrier synchronizations across multiple processing units, particularly in ensuring that compute operations are synchronized before exchange phases, which is crucial for maintaining data consistency in complex or high-volume data processing applications like machine intelligence.
Innovation Solution
An apparatus and method utilizing dedicated hardware and circuitry for propagating synchronization messages, converting signals into packets for transmission over a network, allowing for efficient coordination of barrier synchronizations between processing units by asserting specific signals and detecting changes to manage synchronisation requests and acknowledgments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated hardware circuits are used for synchronisation message propagation, then synchronisation reliability is improved, but device complexity increases
Solution Approach 1:
The system segments synchronisation message propagation into two distinct pathways: a first synchronisation message propagation circuitry for critical synchronisation signals and a second synchronisation message propagation circuitry for other synchronisation communications. This segmentation allows each pathway to be optimised for its specific function, improving overall reliability while managing complexity through functional separation.
Solution Approach 2:
A synchronisation interface is introduced as an intermediary component that couples the first and second synchronisation message propagation circuitries. This interface manages the interaction between the two circuitries, coordinating signal flow and timing, thereby improving synchronisation reliability while containing device complexity through a dedicated mediation layer.
2Measurement precision
If multiple dedicated hardware interfaces are used for different synchronisation signals, then synchronisation precision is improved, but device complexity increases
Solution Approach 1:
The system divides synchronisation signal transmission into multiple dedicated hardware interfaces, with each interface assigned to specific synchronisation signals. This segmentation ensures that critical synchronisation signals receive dedicated transmission paths, improving synchronisation precision while managing complexity through organised functional separation.
Solution Approach 2:
Different hardware interfaces are allocated to different synchronisation signals based on their specific requirements. Critical synchronisation signals that require higher precision are assigned to dedicated interfaces with appropriate timing and transmission characteristics, while less critical signals use other interfaces. This local quality approach optimises precision where needed while controlling overall device complexity.
3Reliability
If barrier synchronisation is implemented between multiple processing units, then data consistency is improved, but loss of time increases
Solution Approach 1:
The system performs preliminary synchronisation actions by propagating synchronisation messages through dedicated hardware circuitries before the actual barrier synchronisation point. This advance notification allows processing units to prepare for the synchronisation event, reducing the actual time required to achieve data consistency while maintaining reliability.
Solution Approach 2:
The first and second synchronisation message propagation circuitries operate continuously to maintain synchronisation state across processing units. By keeping the synchronisation mechanism actively running and ready, the system minimises delays when barrier synchronisation events occur, thereby reducing time loss while ensuring data consistency is maintained.
Data Source
AI summary
An apparatus is provided for converting the form in which a synchronisation request for a barrier synchronisation is provided. The synchronisation request is provided from a first synchronisation circuitry to a second synchronisation circuitry by asserting one of a set of separate signals that may each correspond to a bit in a register or a signal on a wire. The second synchronisation circuitry provides for the packetisation of the sync request by sending a packet comprising the sync request over a network to be received at a further subsystem.