Barrier Synchronization Device for Multi-Core Processor Cores
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current barrier synchronization methods in multi-core processors are hindered by the slower main memory access speed, leading to increased time for coordinated operations and higher power consumption, especially when processor cores within the same synchronization group need to shift to the next process.
Innovation Solution
A barrier synchronization method and device that assigns processor cores to the same synchronization group, allowing them to store synchronization information in memory and transition to a quiescent state after completing a process, reducing the need for external data transmission and enabling faster synchronization by directly writing synchronization information to memory and using dedicated wires for high-speed access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processor cores use main memory for storing synchronization information, then the system can achieve barrier synchronization, but the synchronization time increases due to slower main memory access speed
Solution Approach 1:
The patent divides the memory system into two segments: main memory for general-purpose data storage and a dedicated small-capacity memory (synchronization memory) for storing synchronization information. This segmentation allows synchronization operations to access data from the faster, dedicated memory rather than the slower main memory, thereby reducing synchronization time while maintaining the barrier synchronization capability.
Solution Approach 2:
The patent introduces a dedicated synchronization memory as an intermediary between the processor cores and main memory. This intermediary memory specifically stores synchronization information (such as barrier status and core identifiers) and provides high-speed access for synchronization operations, eliminating the need for processor cores to access main memory for synchronization data.
2Reliability
If processor cores frequently access main memory for synchronization operations, then barrier synchronization can be maintained, but power consumption increases
Solution Approach 1:
By segmenting the memory system into main memory and dedicated synchronization memory, the patent enables synchronization operations to use the smaller, lower-power synchronization memory. This reduces the energy consumption associated with memory access during synchronization operations while maintaining synchronization accuracy.
Solution Approach 2:
The dedicated synchronization memory serves the specific function of storing and providing synchronization information autonomously, without requiring processor cores to access main memory. This self-service capability for synchronization operations reduces overall system power consumption by minimizing high-power main memory accesses.
3Ease of operation
If all processor cores belong to the same synchronization group within one multi-core processor, then coordinated operations can be performed, but the system cannot utilize distributed processing across multiple processors
Solution Approach 1:
The patent designs the synchronization device with universal functionality that can operate in multiple modes: it can synchronize processor cores within a single multi-core processor or across multiple multi-core processors. The synchronization memory and control logic are designed to handle both intra-processor and inter-processor synchronization scenarios, providing adaptability without sacrificing coordinated operation capability.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.