Hardware Barrier Synchronization via Staged Register Pipelining

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Solution Overview

Problem

Existing barrier synchronization technologies face challenges in speeding up processing due to resource locking and sequential execution, leading to inefficiencies in high-performance computing environments where collective communication is prevalent.

Innovation Solution

The proposed solution involves a synchronization device with multiple registers that manage setting information and destination status, allowing for staged processing where resources can be released and reused, enabling overlapping of processing stages through pipeline control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If barrier synchronization is implemented using traditional message passing or notification methods, then synchronization can be achieved among processes, but processing speed is limited due to sequential execution and resource locking

Engineering Contradiction:

Improvebarrier synchronization processing speedVSAvoidprocessing time

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The barrier synchronization device divides synchronization processing into multiple sequential stages, with each stage handled by dedicated hardware circuits. This segmentation allows different stages to be processed in parallel across multiple processes, significantly reducing overall synchronization time compared to traditional sequential message passing methods.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The device pre-allocates and prepares multiple registers and hardware circuits in advance for different processing stages. When barrier synchronization is needed, processes can immediately proceed through pre-configured stages without waiting for resource allocation, reducing latency and improving processing speed.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If hardware resources are locked during barrier synchronization processing to ensure data consistency, then reliability is maintained, but resource utilization decreases and processing efficiency is reduced

Engineering Contradiction:

Improvesynchronization accuracyVSAvoidresource utilization

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

By dividing the synchronization process into multiple stages with dedicated hardware circuits for each stage, the system maintains data consistency within each stage while allowing other stages to proceed simultaneously. This eliminates the need to lock all resources for the entire duration of synchronization, improving resource utilization while maintaining reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The barrier synchronization device acts as an intermediary hardware component that manages resource allocation and data consistency. It uses multiple registers and control circuits to coordinate access to shared resources without requiring processes to directly lock and unlock resources, thereby maintaining reliability while improving productivity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If traditional software-based barrier synchronization is used, then flexibility and adaptability are maintained, but processing speed is insufficient for high-performance computing requirements

Engineering Contradiction:

Improvesynchronization processing speedVSAvoidhardware structure complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The hardware device is segmented into multiple independent stage circuits, each handling a specific portion of the synchronization process. This modular architecture provides the speed of hardware execution while maintaining a level of flexibility similar to software, as each stage can be independently configured and controlled.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The barrier synchronization device is designed with multiple registers and circuits that can handle various synchronization scenarios and data types. The hardware structure supports different barrier synchronization modes and can be configured for different application requirements, providing adaptability comparable to software solutions while delivering hardware-level performance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11829806B2High-speed barrier synchronization processing that includes a plurality of different processing stages to be processed stepwise with a plurality of registers

Publication Date: 2023.11.28 FUJITSU LTD

AI summary

An arithmetic processor performs arithmetic processing, and a synchronization processor, including first registers, performs synchronization processing that includes a plurality of processing stages to be processed stepwise. The arithmetic processor sends, to the synchronization processor, setting information to be used in a predetermined processing stage of the synchronization processing, and instruct the synchronization processor to execute the predetermined processing stage for the arithmetic processing. Each of the first registers includes a setting information management area to manage the setting information received from the arithmetic processor, and a destination status area to store a usage state of each of destination registers which are used in a next processing stage following the predetermined processing stage. The synchronization processor executes the predetermined processing stage by transferring data between the first registers to cause the synchronization processing to proceed to the next processing stage.