Barrier-Layer Via Interconnects With Nitride-Free Ru Line Contacts
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Solution Overview
Problem
Existing copper-based interconnect structures in integrated circuits face challenges with high aspect ratios, resistivity, line-to-line capacitance, damage to surrounding layers, and formation of voids, collapses, and bends during patterning and deposition processes as IC feature sizes shrink.
Innovation Solution
The method involves directly depositing conductive materials over vias to form conductive lines with reduced thickness ratios, using materials like Ru and Co with lower resistivity to reduce aspect ratios and minimize damage during patterning, thereby reducing capacitance and resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper-based interconnect structures are used in multilayer interconnect features, then electrical conductivity is improved, but aspect ratio and resistivity increase while causing damages to surrounding layers and forming voids during patterning and deposition
Solution Approach 1:
The patent changes the material parameter from copper to ruthenium, which has different physical and chemical properties including lower resistivity and better adhesion characteristics. This material substitution resolves the contradiction by maintaining electrical conductivity while improving manufacturing precision during patterning and deposition processes
Solution Approach 2:
The patent employs a composite interconnect structure consisting of multiple layers including ruthenium-containing conductive lines, barrier layers, and dielectric materials. This composite approach allows optimization of each layer's properties to achieve both good electrical conductivity and manufacturing precision
2Reliability
If copper-based interconnect structures are used in multilayer interconnect features, then electrical conductivity is improved, but line-to-line capacitance and damage to surrounding ILD layers increase
Solution Approach 1:
The patent changes the material parameter from copper to ruthenium, which exhibits different chemical reactivity and adhesion properties. Ruthenium causes less damage to surrounding interlayer dielectric layers during deposition and patterning processes while maintaining electrical conductivity
Solution Approach 2:
The patent introduces barrier layers as intermediary structures between the conductive interconnect lines and the surrounding dielectric layers. These barrier layers prevent direct interaction and potential damage between the copper-based interconnect and surrounding ILD layers
3Productivity
If interconnect feature size is reduced to increase functional density, then production efficiency is improved, but void formation, collapse, and bending during patterning and deposition increase
Solution Approach 1:
The patent changes the material parameter to ruthenium, which has superior adhesion properties and forms more structurally stable thin films at reduced dimensions. This material substitution maintains structural integrity during patterning and deposition even as feature sizes decrease to increase functional density
Solution Approach 2:
The patent applies preliminary surface treatment and barrier layer deposition before forming the conductive interconnect lines. These preliminary actions prepare the surface and provide structural support that prevents void formation, collapse, and bending during subsequent patterning and deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates issues like void formation, bending, and capacitance, while improving electrical performance by reducing electron scattering and RC delay in integrated circuits.
Implementation Method 1
depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer
Data Source
AI summary
An interconnect structure includes a via including a first barrier layer and a bulk layer disposed over the first barrier layer, and a conductive line disposed over a top surface of the via. The conductive line includes a conductive layer disposed over a top surface of the bulk layer, and a second barrier layer disposed on sidewalls of the conductive layer. The interconnect structure is free of a nitride layer between the bulk layer and the conductive layer.