Barrierless Interconnects Using Self-Assembled Monolayers
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Solution Overview
Problem
As semiconductor technology advances, the use of copper interconnects in integrated circuits faces challenges due to the need for diffusion barriers, which occupy valuable space and increase resistivity as trench sizes decrease, necessitating a barrierless solution for effective conductivity.
Innovation Solution
The implementation of self-assembled monolayers (SAMs) to facilitate electroless metallization of non-copper metals like cobalt, ruthenium, and platinum, which do not require diffusion barriers, allowing for efficient filling of trenches smaller than 10 nm and maintaining comparable conductivity to copper systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a diffusion barrier is used for copper interconnects, then copper degradation is prevented, but interconnect resistivity increases and conductive area decreases
Solution Approach 1:
The patent extracts and removes the diffusion barrier layer from the interconnect structure by transitioning to barrierless copper plating. This eliminates the harmful barrier layer that occupies space and increases resistivity, while maintaining copper reliability through alternative plating techniques that achieve sufficient adhesion and protection without the traditional barrier
Solution Approach 2:
The patent changes the plating parameters and chemistry to enable direct copper deposition without a barrier layer. This involves modifying the electroplating or electroless plating process parameters, such as using specific bath compositions, temperatures, and deposition rates that allow copper to deposit directly on the underlying layer with adequate adhesion and uniformity
2Productivity
If trench size is reduced for downscaling, then device density increases, but diffusion barrier occupies higher percentage of space
Solution Approach 1:
The patent removes the diffusion barrier layer entirely from the scaled-down trench structure, eliminating the space-consuming barrier that would otherwise occupy a significant percentage of the reduced trench area, thereby maximizing the conductive copper area ratio
Solution Approach 2:
The patent applies local quality changes by modifying only the interconnect region to be barrierless while maintaining other structural integrity through localized plating control, allowing the copper to directly contact the underlying layer in specific areas where adhesion is achieved through process optimization
3Reliability
If diffusion barrier is used, then copper diffusion is prevented, but available conductive space is reduced
Solution Approach 1:
The patent extracts and eliminates the diffusion barrier layer, allowing copper to occupy the full trench area for maximum conductive cross-section, while relying on the inherent diffusion resistance of the underlying layer and controlled plating processes to prevent copper degradation
Solution Approach 2:
The patent uses composite material strategies by combining barrierless copper plating with underlying layers that provide inherent diffusion resistance, creating a multi-functional structure where the copper interconnect and underlying layer work together to achieve both high conductivity and diffusion protection without a separate barrier layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the realization of the largest conductive area at smallest dimensions without the need for diffusion barriers, achieving conductive characteristics comparable to copper systems while minimizing liner size, thus addressing the space and resistivity issues associated with traditional copper interconnects.
Implementation Method 1
self-assembled monolayers (SAMs) to facilitate electroless metallization
Implementation Method 2
electroless metallization of non-copper metals like cobalt, ruthenium, and platinum
Data Source
AI summary
Embodiments of the disclosure are directed to using a SAM liner to promote electroless deposition of metal for integrated circuit interconnects. The SAM liner can be formed on a dielectric substrate. A protective layer can be formed on the SAM liner. The protective layer can double as a seed layer for electroless deposition of an interconnect metal. The interconnect metal can be deposited on the protective layer using electroless deposition. The dielectric, with the SAM liner, the protective layer, and the interconnect metal can be annealed to reflow the interconnect metal into trenches formed in the dielectric.