Barrier-Less Via Liner Structure for Low-Resistance Interconnects
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Solution Overview
Problem
The challenge in forming semiconductor devices is the high resistance of interconnect structures, which hinders efficient signal and power routing due to the use of nitride-based barrier layers in via structures, particularly in deep vias within integrated circuits.
Innovation Solution
The formation of low-resistance via structures without nitride-based barrier layers, using a conductive liner and fill made of pure elemental metals like tungsten or molybdenum, deposited using ionized physical vapor deposition (PVD) and chemical vapor deposition (CVD) respectively, ensuring enhanced adhesion and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nitride-based barrier layers are used in via structures, then adhesion and electromigration resistance are improved, but electrical resistance increases
Solution Approach 1:
The patent removes the nitride-based barrier layer from the via structure, extracting the harmful high-resistance element while maintaining adhesion through alternative means (conductive liner material selection and deposition processes). This directly resolves the contradiction by eliminating the source of electrical resistance while preserving reliability functions through the conductive liner design.
Solution Approach 2:
The patent changes the material parameter from nitride-based barrier layer to pure elemental metal conductive liner, fundamentally altering the electrical resistance characteristic while maintaining adhesion through controlled deposition parameters and liner thickness optimization.
2Adaptability or versatility
If via structures are made deeper to route signals in densely packed devices, then routing capability is improved, but resistance increases due to longer conductive path
Solution Approach 1:
The patent changes the material composition parameter from nitride-containing barrier layers to pure elemental metals, fundamentally altering the resistivity characteristic. This allows deeper vias to maintain lower resistance because the conductive liner material itself has superior electrical conductivity properties.
Solution Approach 2:
The patent uses composite construction with conductive liner and conductive fill materials, creating a via structure where both components contribute to low resistance. The conductive liner provides adhesion and initial conductivity, while the conductive fill provides bulk conductivity, together enabling low-resistance deep via routing.
3Object-affected harmful factors
If conductive liner and fill are made of pure elemental metals, then electrical conductivity is improved, but manufacturing complexity increases due to specialized deposition processes
Solution Approach 1:
The patent replaces traditional CVD-based barrier layer deposition with ionized PVD processes for conductive liner formation. This substitution enables pure elemental metal deposition with better adhesion properties and controlled thickness, achieving superior electrical conductivity while managing manufacturing complexity through process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher conductivity via structures with reduced resistance, enabling more efficient signal and power routing in densely packed semiconductor devices, thereby improving the performance and viability of integrated circuits.
Implementation Method 1
The conductive liner may be an elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy with no metal nitride or barrier layer present between the conductive liner and the dielectric wall. In some such examples, the conductive liner is a first metal (e.g., molybdenum) deposited by a first deposition process (e.g., physical vapor deposition, PVD)
Implementation Method 2
the conductive fill is a second metal (e.g., tungsten) deposited by a second deposition process (e.g., chemical vapor deposition or atomic layer deposition, CVD or PVD)
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
Techniques to form low-resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. The via may include a conductive portion that extends through a dielectric wall in a third direction along at least an entire thickness of the gate structure. The conductive portion includes a conductive liner directly on the dielectric wall and a conductive fill on the conductive liner. The conductive liner comprises a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy, with no metal nitride or barrier layer present between the conductive liner and the dielectric wall.