Barrier-Less Via Plug Structure for Low-Resistance Thermal Stability
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Solution Overview
Problem
Traditional via plugs in semiconductor integrated circuits (ICs) exhibit increased resistance and unsuitability as they scale down, necessitating a new plug structure with lower electrical resistance and improved thermal stability.
Innovation Solution
The introduction of a barrier-less plug structure comprising a first metal with multiple grains and a second metal distributed along the grain boundaries and interfaces, stabilized through annealing or ion implantation to enhance thermal stability and reduce defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional via plugs with barrier layers are used, then thermal stability is improved, but electrical resistance increases
Solution Approach 1:
The patent removes the barrier layer from the plug structure entirely, extracting the problematic component that caused high electrical resistance. The plug consists only of metal filling the via hole without any barrier layer, directly solving the resistance issue while maintaining thermal stability through proper metal selection and processing.
Solution Approach 2:
The patent changes the material parameters by selecting specific metals (such as tungsten, cobalt, copper, or aluminum) with appropriate electrical and thermal properties. By adjusting metal grain size, orientation, and purity through controlled deposition and annealing processes, the patent achieves low electrical resistance while maintaining thermal stability without requiring a barrier layer.
2Productivity
If via plugs are scaled down, then production efficiency is improved, but electrical resistance increases
Solution Approach 1:
The patent changes physical parameters including metal grain size, crystal orientation, and density by controlling deposition conditions and annealing parameters. These parameter changes enable the plug to maintain low electrical resistance even at reduced dimensions, allowing continued scaling while preserving electrical performance.
Solution Approach 2:
The patent employs composite metal structures with specific grain distributions and orientations within the plug. By creating a composite microstructure with varying grain sizes and orientations, the patent achieves optimized electrical properties that maintain low resistance in scaled-down via plugs.
3Manufacturing precision
If barrier-less plug structure is used, then electrical resistance is reduced, but structural integrity during thermal processes deteriorates
Solution Approach 1:
The patent changes material parameters by selecting metals with appropriate melting points and thermal stability characteristics. Through controlled annealing processes, the patent optimizes grain size and distribution to enhance structural integrity. The metal is processed to achieve a microstructure that resists deformation and maintains integrity during subsequent thermal processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The barrier-less plug structure provides lower electrical resistance and maintains structural integrity during subsequent thermal processes, preventing defects such as pitting and grooving, thereby enhancing the reliability and performance of ICs.
Implementation Method 1
annealing or ion implantation to enhance thermal stability
Implementation Method 2
The second metal may be introduced into the first metal by a deposition process or an ion implantation process, followed by an annealing process
Data Source
AI summary
A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.