Barycenter Compact Modeling for Hierarchical IR Drop Simulation
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Solution Overview
Problem
Existing circuit simulation algorithms struggle with large, complex integrated circuits due to parasitic effects, leading to poor simulation results, increased computational resources, and inefficiencies in handling hierarchical designs, especially in distributed computing environments.
Innovation Solution
A Barycenter compact model and hierarchical scheduler are employed to solve large circuit networks in a multicore and distributed computing environment, utilizing I/O slicing and hierarchical boundary conditions to manage memory usage and job dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing circuit simulation algorithms are used for large integrated circuits, then simulation results are obtained, but computational resources increase and simulation efficiency decreases
Solution Approach 1:
The circuit network is divided into multiple sub-circuits or modules, each simulated independently or in parallel. This segmentation reduces the computational burden on single processors and enables distributed computing approaches, thereby improving simulation efficiency while maintaining accuracy through proper handling of inter-module connections
Solution Approach 2:
The simulation approach transitions from single-threaded sequential processing to multi-threaded parallel processing across multiple processors or computing nodes. This dimensional change in computational architecture allows simultaneous execution of simulation tasks, significantly improving productivity without sacrificing measurement precision
2Measurement precision
If parasitic effects are considered in circuit simulation, then simulation accuracy improves, but computational complexity increases
Solution Approach 1:
Parasitic effects are modeled with varying levels of detail depending on the specific circuit region or component. Critical areas with significant parasitic impacts use detailed models, while less critical areas use simplified models. This selective approach maintains simulation accuracy where needed while reducing overall computational complexity
Solution Approach 2:
The simulation methodology dynamically adjusts parasitic model parameters and inclusion levels based on circuit characteristics, frequency range, and design requirements. This adaptive parameter adjustment allows the simulation to account for parasitic effects when necessary while avoiding unnecessary computational overhead in scenarios where parasitics are negligible
3Device complexity
If hierarchical designs are handled in distributed computing environments, then design complexity is managed, but job dependency management becomes more difficult
Solution Approach 1:
The hierarchical scheduler pre-processes the circuit netlist to identify hierarchical boundaries, data dependencies, and computation workflows before simulation begins. This preliminary analysis creates a structured execution plan that explicitly defines job dependencies and data flow between hierarchical levels, making distributed computing coordination more manageable
Solution Approach 2:
The hierarchical scheduler acts as an intermediary layer between the distributed computing resources and the hierarchical circuit design. It manages job submission, tracks dependencies across hierarchical boundaries, coordinates data exchange between levels, and balances computational loads, thereby simplifying the complexity of operating distributed systems on hierarchical designs
Data Source
AI summary
Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A boundary condition between blocks is formulated by the Barycenter compact model. Boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.