Base Address Sorting in PCI Express Serial Switches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the number of external devices connected to PCI Express systems increases, conventional PCI Express serial switches require an exponentially growing number of comparators and registers, leading to increased chip space usage, power consumption, and latency.
Innovation Solution
A novel method and device for base address sorting and entry into base address registers, utilizing an array of shadow registers and control logic circuitry to rapidly sort and insert new base addresses without the need for a large number of comparators, allowing for efficient handling of a large number of ports without exponential growth in hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PCI Express serial switch architecture is used to accommodate more external devices, then the number of supported external devices increases, but the number of comparators and registers grows exponentially, leading to increased chip space usage, power consumption, and latency
Solution Approach 1:
The patent segments the base address register array into multiple smaller groups, with each group managed by a dedicated sorting device. This segmentation allows the switch to handle more external devices without requiring a proportional increase in comparators, as each sorting device independently manages its segment using efficient insertion sort algorithms
Solution Approach 2:
The patent implements preliminary sorting of base addresses before comparison operations. By pre-sorting the base address registers into ascending or descending order using insertion sort, the system eliminates the need for multiple comparators during packet routing, as the sorted structure enables efficient binary search and direct comparison
2Measurement precision
If more comparators are added to handle more external devices, then address comparison capability improves, but chip space consumption and power consumption increase
Solution Approach 1:
The patent changes the organizational parameter of base address registers from unsorted to sorted order, and divides the large register array into smaller segments. This parameter change enables the use of fewer comparators while maintaining address comparison capability, as the sorted structure allows for efficient binary search and reduced comparison operations
3Measurement precision
If more comparators are used to support more ports, then address matching accuracy improves, but system latency increases
Solution Approach 1:
By segmenting the base address register array into smaller groups managed by individual sorting devices, the patent reduces the time required for address comparison. Each sorting device handles a subset of addresses independently, parallelizing the comparison process and reducing overall system latency while maintaining address matching accuracy
4Adaptability or versatility
If the number of base address registers is increased to accommodate more external devices, then device connectivity improves, but the number of required comparators grows exponentially
Solution Approach 1:
The patent applies preliminary sorting to base address registers before they are used for packet routing decisions. By pre-organizing the base addresses in sorted order within segmented groups, the system enables efficient address matching with fewer comparators, allowing increased device connectivity without exponential growth in comparator requirements
Data Source
AI summary
A base address sorting device in a serial switch is disclosed which includes an array of shadow registers, each shadow register in the array being electrically coupled to a base address register, in an array of base address registers, each of the base address registers having a base address, and control logic circuitry electrically coupled to the array of shadow registers and to the array of base address registers with the control logic circuitry being operable, when it receives a configuration command, to implement a method, for reconfiguring the contents of the array of base address registers, including: inserting a new base address from the configuration command into a shadow register in the array of shadow registers, sorting the array of shadow registers into a predetermined order, and then copying the contents of the array of shadow registers into the array of base address registers.