Base Die Error Correction for Memory Reliability

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Solution Overview

Problem

In semiconductor memory systems, the lack of error checking and correction functionality in the base die leads to increased die area requirements for processors and memory dies, affecting performance and storage reliability due to the need for error detection and correction by the processor or core dies.

Innovation Solution

Incorporating error checking and correction capabilities into the base die, which performs ECC encoding and decoding processes during data transmission, reducing the burden on processors and memory dies by managing and correcting errors within the base die.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error checking and correction functionality is implemented in the processor or memory die, then data reliability is improved, but die area requirements increase

Engineering Contradiction:
Improvedata reliabilityVSAvoiddie area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent introduces a base die as an intermediary component between the processor and memory die. This base die contains the error checking and correction circuitry, acting as a mediator that handles data validation without requiring the processor or memory die to incorporate these functions directly. The base die receives data from the processor, performs ECC operations, and then transmits validated data to the memory die, thereby improving data reliability while keeping the processor and memory die areas unchanged.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If error checking and correction functions are integrated into the base die, then system reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the memory system into three separate functional components: the processor, the base die, and the memory die. By segmenting the system architecture and placing error checking and correction functionality specifically in the base die, the patent improves system reliability through dedicated ECC operations while managing device complexity through functional separation. Each component has a specialized role, preventing the complexity from being concentrated in a single component.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the base die performs ECC encoding and decoding, then data transmission reliability is improved, but the burden on processors and memory dies increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidprocessing burden
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The base die serves as an intermediary that assumes the burden of ECC encoding and decoding operations. Instead of requiring the processor or memory die to perform these error correction functions, the base die intercepts data transmissions, performs the necessary ECC operations, and passes the validated data along. This redistribution of processing burden to the base die improves data transmission reliability while preventing the processor and memory die from being overloaded with error correction responsibilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11983416B2Base die, memory system, and semiconductor structure
Publication Date: 2024.05.14 CHANGXIN MEMORY TECH INC
  • US11983416B2 patent drawing
  • US11983416B2 patent drawing
  • US11983416B2 patent drawing

AI summary

A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performing a first error correction code encoding processing on the first data, and transmit second data to a memory die in the writing phase, wherein the second data includes a first data after the first error checking and correction processing; the base die is further configured to receive the second data from the memory die in a reading phase, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading phase, wherein the third data includes the second encoded data and the first data after the first error checking and correction processing.