Base Die Bus Architecture for Parallel Host-Memory Links
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Solution Overview
Problem
Conventional computing systems face inefficiencies in connecting host devices and memory apparatuses, particularly when they are manufactured as chiplets, due to the need for additional circuits like SerDes and limitations in data bandwidth and signal integrity as frequency increases.
Innovation Solution
A computing system architecture that includes a base die with overlapping circuit blocks, a stacked memory structure, and multiple signal transmission paths, allowing for integrated circuit packages to perform parallel data communication without additional circuits like SerDes, thereby increasing data bandwidth and reducing physical constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If serial data transmission is used to minimize the number of data signal transmission lines, then the number of transmission lines is reduced and skew between data signals and clock signals is reduced, but additional circuits like SerDes are required which increases device complexity
Solution Approach 1:
The base die is divided into multiple circuit blocks (first circuit block, second circuit block, etc.) that are spatially separated and functionally independent. Each circuit block can be independently connected to different memory stacks, enabling parallel data transmission paths that reduce the need for complex serialization/deserialization circuits while maintaining minimal transmission lines.
Solution Approach 2:
The patent transitions from a two-dimensional planar connection architecture to a three-dimensional stacked architecture. Memory stacks are positioned at different locations on the base die and connected through vertical interconnects, creating multiple spatial dimensions for data transmission. This dimensional change enables parallel communication paths without requiring additional complex circuits.
2Adaptability or versatility
If the host device and memory apparatus are manufactured as chiplets to increase integration density, then manufacturing flexibility and integration capacity are improved, but the need for additional connection circuits and limitations in data bandwidth arise
Solution Approach 1:
The patent implements a three-dimensional stacked architecture where multiple memory stacks are vertically positioned over different circuit blocks on the base die. This vertical stacking enables parallel data transmission paths in the third dimension, significantly increasing data bandwidth while maintaining chiplet-based manufacturing flexibility.
Solution Approach 2:
The base die is segmented into multiple independent circuit blocks that can be separately manufactured as chiplets. Each circuit block is independently connected to specific memory stacks, allowing for modular assembly and parallel data transmission, thereby increasing overall data bandwidth while maintaining manufacturing flexibility.
3Speed
If frequency is increased to improve data transmission speed, then data transmission speed is improved, but signal integrity deteriorates
Solution Approach 1:
The patent utilizes vertical interconnects through the substrate to connect circuit blocks with memory stacks positioned at different heights. This three-dimensional arrangement shortens the horizontal signal transmission distance while maintaining high frequency operation, thereby preserving signal integrity at high data transmission speeds.
Solution Approach 2:
The substrate serves as an intermediary structure that provides controlled impedance pathways for signal transmission between circuit blocks and memory stacks. The substrate's structured interconnects act as mediators that maintain signal integrity by controlling electromagnetic field distribution during high-frequency data transmission.
Data Source
AI summary
A computing system includes a base die, a host device, and a stacked memory structure. The base die has a first surface and a second surface and includes a first circuit block and a second circuit block. The host device is disposed to overlap at least a portion of the first circuit block of the base die. The stacked memory structure is disposed to overlap at least a portion of the second circuit block of the base die. The host device and the first circuit block of the base die are coupled through a first signal transmission path. Between the first circuit block and the second circuit block, and between the second circuit block and the stacked memory structure, coupling is made through a second signal transmission path.