Base Epitaxy Blocking Features for Low-Leakage Source/Drain Growth
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Solution Overview
Problem
Existing semiconductor technologies face challenges in forming high-quality source/drain portions that induce channel strain effectively, leading to potential current leakage and reduced transistor performance.
Innovation Solution
The formation of blocking features within base epitaxy layers using ion implantation to dope dopants at high temperatures, ensuring the upper surfaces of the epitaxy layers maintain a single crystal structure, which allows for the growth of high-quality source/drain portions with reduced voids and improved current blocking properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If blocking features are formed in base epitaxy layers to prevent current leakage, then transistor performance is improved, but the crystal structure of the epitaxy layers may be damaged
Solution Approach 1:
The patent applies local quality by creating blocking features only in specific regions of the base epitaxy layers where current blocking is needed, while preserving the single crystal structure in the upper surfaces that will serve as growth substrates for source/drain portions. This localized approach allows different regions of the same epitaxy layer to have different functions - one region for blocking current leakage and another for maintaining crystal quality for subsequent growth.
Solution Approach 2:
The patent segments the base epitaxy layers into distinct functional zones: regions with blocking features formed through ion implantation and regions with preserved single crystal structure. This segmentation allows the blocking features to be confined to specific areas while leaving other areas intact for source/drain growth, thus resolving the contradiction between current blocking and crystal structure preservation.
2Manufacturing precision
If ion implantation is performed at high temperatures to form blocking features, then dopant diffusion is enhanced, but thermal damage to the epitaxy layers may occur
Solution Approach 1:
The patent utilizes parameter changes by performing ion implantation at elevated temperatures (e.g., 600-900°C) to enhance dopant diffusion and achieve desired dopant distribution profiles. The temperature parameter is carefully controlled and optimized to ensure sufficient dopant activation and diffusion while avoiding excessive thermal damage to the epitaxy layers, thus resolving the contradiction between dopant distribution control and thermal damage risk.
3Reliability
If source/drain portions are formed by epitaxy growth on base epitaxy layers, then high-quality single crystal source/drain portions are achieved, but current leakage through the base epitaxy layers occurs
Solution Approach 1:
The patent applies preliminary action by forming blocking features within the base epitaxy layers before growing the source/drain portions. This advance preparation ensures that when the source/drain portions are subsequently formed by epitaxy growth on the base epitaxy layers, the blocking features are already in place to prevent current leakage, thus resolving the contradiction between achieving high-quality single crystal source/drain portions and preventing current leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the quality of source/drain portions, reducing current leakage and maintaining single crystal structure, thereby improving transistor performance and channel strain.
Implementation Method 1
performing an ion implantation process to dope dopants into the base epitaxy layers
Implementation Method 2
performing an ion implantation process to dope dopants into the base epitaxy layers at a relatively high temperature, e.g., not less than 500° C., so as to retain the upper surfaces including silicon with single crystal structure
Implementation Method 3
Source/drain portions in the semiconductor structure are formed by epitaxy growth of a silicon-based semiconductor material directly on upper surfaces of the base epitaxy layers
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: forming stacks on a substrate; forming gate structures on the stacks, portions of the stacks are exposed from the gate structures; forming trenches respectively in the portions of the stacks and respectively extending into upper portions of the substrate, after forming the trenches, each of the stacks being formed into stack portions each including first nanosheets, and second nanosheets that alternate with the first nanosheets; forming base epitaxy layers respectively at bottoms of the trenches; performing an ion implantation process to obtain doped base epitaxy layers, each of which is embedded with a blocking feature; and forming source/drain portions respectively in the trenches on the doped base epitaxy layers such that each of the source/drain portions is isolated from the substrate through the blocking feature in a respective one of the doped base epitaxy layers.