Base Leads for Semiconductor Stacking via Substrate Etching
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Solution Overview
Problem
Current vertical interconnect structures for stacking semiconductor devices are costly, time-consuming, and prone to defects such as stress, cracking, and collapse during manufacturing.
Innovation Solution
The formation of electrically isolated base leads from a common base substrate, with conductive layers on opposing surfaces, allows for a simple and cost-effective vertical interconnect structure for stacking semiconductor devices, providing both electrical connection and structural support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional vertical interconnect structures (TSV, THV, conductive pillars, conductive bumps) are used for stacking semiconductor devices, then electrical interconnection between multiple levels is achieved, but the manufacturing process becomes costly and time-consuming with high susceptibility to stress, cracking, and collapse defects
Solution Approach 1:
The patent extracts and removes the problematic intermediate vertical interconnect structures (TSV, THV, conductive pillars, conductive bumps) from the stacking process. Instead, it directly connects semiconductor dies to the base substrate using wire bonds, eliminating the complex and defect-prone intermediate structures while simplifying the manufacturing process and improving reliability
Solution Approach 2:
The patent inverts the conventional approach by establishing wire bond connections from the die level directly to the base substrate, rather than building up complex vertical interconnect structures first. This reversal of the manufacturing sequence eliminates the need for TSV, THV, and conductive pillars, reducing process complexity and defects
2Productivity
If conventional vertical interconnect structures are used for 3-D device integration, then electrical interconnection is achieved, but manufacturing cost and time increase significantly
Solution Approach 1:
The patent removes the time-consuming steps of forming TSV, THV, conductive pillars, and conductive bumps from the manufacturing process. By directly implementing wire bond connections from dies to the base substrate, it significantly reduces manufacturing cycle time and improves productivity while maintaining electrical interconnection functionality
Solution Approach 2:
The patent inverts the conventional manufacturing sequence by establishing wire bond connections early in the process rather than completing complex vertical interconnect structures first. This reversal eliminates multiple fabrication steps, reducing both manufacturing time and cost while achieving the same electrical interconnection goal
Data Source
AI summary
A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die.