Base-Offset Load/Store Addressing for Parallel Memory Access

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Graphics processor and compute accelerator kernel programs experience a significant increase in computational inefficiency due to additional instructions added for address calculations when accessing elements of an array in memory, which reduces their performance.

Innovation Solution

Implementing hardware enhancements in load/store instructions to perform automatic offset scaling, offloading address calculations to the load/store circuitry instead of primary execution resources, thereby optimizing memory access operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional instructions are added to perform address calculations in kernel programs, then memory access capability is improved, but computational efficiency deteriorates

Engineering Contradiction:

Improvememory access capabilityVSAvoidcomputational efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent extracts the address calculation function from the primary execution resources (kernel program instructions) and relocates it to dedicated load/store circuitry. This separation allows the kernel program to remain simple while the hardware automatically handles address calculations, thus improving computational efficiency without sacrificing memory access capability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces load/store instructions as an intermediary layer between the kernel program and memory access operations. These instructions carry base addresses and offsets, and the load/store circuitry automatically performs the address calculation and memory access, eliminating the need for explicit address calculation instructions in the kernel program.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If address calculations are performed by primary execution resources, then flexibility in addressing is maintained, but instruction execution time increases

Engineering Contradiction:

Improveaddressing flexibilityVSAvoidinstruction execution time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent performs address calculations in advance by having the load/store circuitry automatically compute the effective address from the base address and offset before the actual memory access occurs. This preliminary action eliminates the need for sequential instruction execution for address calculation, thereby reducing instruction execution time while maintaining addressing flexibility.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The load/store circuitry is designed to automatically perform address calculations without requiring explicit instructions from the kernel program. The circuitry takes base addresses and offsets as inputs and self-services the address computation and memory access operations, reducing the instruction overhead while preserving addressing capabilities.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20250348321A1Base plus offset addressing for load/store messages

Publication Date: 2025.11.13 INTEL CORP

AI summary

Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.