Semiconductor Base Plate Test Layout for SADP Resistivity Measurement
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Solution Overview
Problem
The integration density of semiconductor memory devices is limited by the restrictions of lithography equipment, necessitating innovative methods to enhance pattern formation and testing for high-capacity devices.
Innovation Solution
A semiconductor base plate with a test region featuring a self-aligned double patterning (SADP) process, including conductive layers and insulating layers with test structures and lines, allows for the determination of resistivity by loading different voltages through test pads and pads connected via holes, enabling efficient testing and pattern formation beyond lithography limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography equipment is used for pattern formation, then the manufacturing process is simple and well-established, but the integration density of semiconductor memory devices is limited
Solution Approach 1:
The pattern formation process is divided into multiple stages through self-aligned double patterning (SADP). The mandrel structure is formed first, then spacer structures are added around it, creating multiple patterns from a single lithography step. This segmentation allows achieving higher integration density by forming finer patterns than traditional single-step lithography can produce.
Solution Approach 2:
Mandrel structures are formed in advance as templates before the final pattern is created. These preliminary mandrels guide the subsequent spacer formation and pattern transfer processes, enabling precise pattern definition that overcomes lithography resolution limits and achieves higher integration density.
2Measurement precision
If more test structures and measurement points are added to determine resistivity accurately, then the measurement precision improves, but the device complexity increases
Solution Approach 1:
The test structures are designed to serve multiple functions: they test the conductive layer properties, verify pattern formation quality, and measure resistivity characteristics. By integrating these multiple testing functions into a unified test structure design, the patent achieves comprehensive measurement capabilities without proportionally increasing device complexity.
Solution Approach 2:
Test pads and contact structures serve as intermediaries between the measurement equipment and the conductive layers. These intermediary elements enable accurate resistivity measurements by providing accessible connection points, while their standardized design prevents excessive complexity in the overall test structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the precise determination of resistivity in test lines, facilitating the formation of high-integration semiconductor devices and improving the integration density of memory devices without the limitations of traditional lithography.
Implementation Method 1
a first conductive layer, located in the test region of the semiconductor substrate, wherein the first conductive layer includes a first test structure and a second test line arranged at intervals from each other... the third test pad is electrically connected to a first terminal of the second test line through a first via hole, and the fourth test pad is electrically connected to a second terminal of the second test line through a second via hole
Implementation Method 2
determining a resistivity of the first test line by loading different voltages to the first test pad and the second test pad through a test machine; and after forming the second conductive layer in the test region of the semiconductor substrate, determining a resistivity of the second test line by loading different voltages to the third test pad and the fourth test pad through the test machine
Data Source
AI summary
The embodiments of the present disclosure provide a semiconductor base plate and a test method thereof. When a first test line and a second test line in the semiconductor base plate are tested, a resistivity of the first test line can be tested by directly loading voltages to a first test pad and a second test pad after a first conductive layer is formed and before a first insulating layer is formed. After a second conductive layer is formed, a resistivity of the second test line is tested by loading voltages to a third test pad and a fourth test pad.