Self-aligned Base Polysilicon Register Structure
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Solution Overview
Problem
In the double-polysilicon self-alignment technology for silicon-based bipolar transistors, there is a challenge in maintaining the intrinsic region protection between the base polysilicon and the silicon substrate, leading to inconsistent electric parameters due to register offset issues caused by the SiO2 protective layer, which affects the device's frequency performance and noise characteristics.
Innovation Solution
A self-aligned register structure for base polysilicon is developed, featuring a partially oxidized silicon substrate with a SiO2 medium protective layer and symmetrical base polysilicon layers on either side, where the silicon substrate is lightly etched between the SiO2 and polysilicon layers to control diffusion and ensure precise alignment, thereby eliminating physical or chemical damage during etching and improving register accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a SiO2 protective layer is used to protect the intrinsic region during base polysilicon etching, then the intrinsic region is protected from damage, but the register between the base polysilicon and SiO2 protective layer becomes difficult to control, leading to register offset issues
Solution Approach 1:
A thin SiO2 medium layer (50-100 nm) is introduced as an intermediary between the base polysilicon and the SiO2 protective layer. This intermediate layer serves as a reference for etching termination, enabling precise register control while maintaining intrinsic region protection. The SiO2 medium layer acts as a mediator that resolves the conflict between protection and precision by providing a controllable etching stop point.
Solution Approach 2:
The SiO2 medium layer is formed in advance before the base polysilicon deposition and etching processes. This preliminary action establishes a predetermined reference structure that guides subsequent etching operations, ensuring that the base polysilicon is etched to the correct depth and position relative to the SiO2 protective layer, thereby achieving both protection and precision.
2Reliability
If the SiO2 protective layer size is increased to ensure coverage, then the intrinsic region is better protected, but the base polysilicon overlaps in the SiO2 protective layer, making register conditions unmeasurable
Solution Approach 1:
The SiO2 medium layer serves as an intermediary reference structure that enables register measurement. By providing a distinct, measurable interface between the base polysilicon and the SiO2 protective layer, it allows process engineers to verify register alignment during manufacturing, thus resolving the measurement difficulty while maintaining adequate protection coverage.
Solution Approach 2:
The different materials (base polysilicon, SiO2 medium layer, SiO2 protective layer) have distinct etching rates and physical properties that create measurable differences during the etching process. These material property differences act as 'color changes' or visual/physical indicators that enable register condition detection and measurement.
3Manufacturing precision
If the SiO2 protective layer size is reduced to improve register control, then the register requirement becomes more stringent, but the SiO2 layer may not be able to protect the intrinsic region or may overlap with the base polysilicon
Solution Approach 1:
The protective structure is segmented into two distinct SiO2 layers: the SiO2 medium layer (50-100 nm) that provides register control functionality, and the SiO2 protective layer that provides intrinsic region protection. This segmentation allows each layer to be optimized for its specific function, achieving both precise register control and reliable protection without the trade-off present in the single-layer approach.
Solution Approach 2:
The SiO2 medium layer acts as an intermediary that decouples the register control function from the protection function. By providing a dedicated reference structure separate from the protective layer, it enables relaxed register requirements while maintaining adequate protection, as the two functions are no longer coupled in a single layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves an extremely high register requirement, ensuring consistent electric parameters and reducing capacitance, while being simple, cost-effective, and time-efficient, thereby enhancing the frequency performance and noise characteristics of silicon-based bipolar transistors.
Implementation Method 1
oxidizing to form a SiO2 medium protective layer on a silicon substrate
Implementation Method 2
the silicon substrate between the SiO2 medium protective layer and the adjacent base polysilicon layers at both sides is lightly etched
Data Source
AI summary
The present invention discloses a self-aligned register structure for base polysilicon and a preparation method thereof. The self-aligned register structure comprises a silicon substrate having a partially oxidized region of SiO2 medium, a SiO2 medium protective layer is arranged at a center above the silicon substrate, base polysilicon layers are located at left and right sides of the SiO2 medium protective layer, the adjacent base polysilicon layers are symmetrical to the SiO2 medium protective layer at equal spacing, and the spacing is equal to a thickness of the base polysilicon layer. The self-aligned register structure for base polysilicon of the present invention meets an extremely high register requirement, guarantees the uniformity of electric parameters of devices, and eliminates physical or chemical damage to an intrinsic region when etching a surface of the silicon substrate during the forming of the base polysilicon, thus reducing the capacitance and enhancing the product yield; and meanwhile, the preparation method is simple, convenient, low in cost, and short in time.