Base Station Buffer Architecture for PDCP RLC Latency

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Solution Overview

Problem

Existing base station architectures require multiple buffers for PDCP and RLC processing, leading to resource inefficiency, high processing latency, and complex flow control, which can result in buffer overflow or underflow, and make it difficult to maintain high throughput under varying radio conditions.

Innovation Solution

Implementing a combined buffer for PDCP and RLC processing that performs partial or full pre-processing of data packets, storing processed packets until requested by the radio link controller, thereby eliminating the need for separate buffers and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple separate buffers are provided for PDCP and RLC processing, then data transmission reliability is maintained, but device complexity and resource usage increase

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidbuffer architecture complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the PDCP buffer and RLC buffer into a single shared buffer structure. The PDCP logic and RLC logic both access the same buffer memory space, eliminating the need for separate buffer allocations. This reduces device complexity and resource usage while maintaining data transmission reliability through coordinated access control between the two logic components.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared buffer serves multiple functions simultaneously: it acts as both the PDCP buffer for packet data convergence protocol operations and the RLC buffer for radio link controller operations. This multi-functional buffer design reduces the overall number of buffers needed in the system while maintaining all necessary data storage capabilities for both processing layers.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Loss of time

If data packets are processed immediately by PDCP logic, then processing latency is reduced, but buffer overflow risk increases when radio link is slow

Engineering Contradiction:
Improveprocessing latencyVSAvoidbuffer overflow prevention
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent implements feedback control through RLC-PDCP flow control mechanisms. The RLC logic monitors buffer occupancy and provides feedback to the PDCP logic to regulate the rate of data packet processing. When the buffer approaches full capacity, the feedback signal slows down PDCP processing, preventing buffer overflow while still allowing rapid processing when buffer space is available, thus managing latency dynamically.

Inventive Principle:
Principle #23Feedback

3Reliability

If RLC-PDCP flow control is implemented to prevent buffer overflow, then buffer reliability is improved, but flow control parameter optimization becomes difficult

Engineering Contradiction:
Improvebuffer overflow preventionVSAvoidflow control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs dynamic parameter adjustment in the flow control mechanism. The flow control parameters are not fixed but are adapted based on buffer occupancy levels and radio conditions. This allows the system to optimize throughput under various radio conditions while maintaining buffer overflow prevention, making the flow control more adaptable and easier to optimize across different operating scenarios.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2477365B1Transmission of encoded data packets
Publication Date: 2015.03.11 ALCATEL LUCENT SA
  • EP2477365B1 patent drawingFigure 1~2

AI summary

A base station operable to transmit encoded data packets, a method and a computer program product are disclosed. The base station is operable to transmit encoded data packets to user equipment. The base station comprises: packet data convergence protocol logic operable to generate packet data convergence protocol encoded data packets from received data packets; and radio link controller logic operable to generate radio link controller encoded data packets for transmission to user equipment from said packet data convergence protocol encoded data packets, said packet data convergence protocol logic comprising: processing logic operable to perform at least partial packet data convergence protocol processing on said received data packets; and a packet data convergence protocol buffer operable to store data packets subjected to said at least partial packet data convergence protocol processing to be provided in response to a request from said radio link controller logic. It will be appreciated that this can significantly reduce the amount of buffer space that may be required. Also, by pre-processing the data packets, the latency of any request from the radio link controller for data packets is significantly reduced, which reduces the likelihood of an available scheduling slot being missed.