Baseband IC Digital Interface RFIC Synchronization Latency
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Solution Overview
Problem
Wireless communication devices face increased chip manufacturing costs and performance deterioration due to analog interfaces between radio frequency integrated circuits (RFIC) and baseband modems, and digital interfaces introduce latency issues with variable timing factors.
Innovation Solution
A baseband integrated circuit (IC) with a digital interface that receives sampled signals from an RFIC, reconstructs them, and transfers them to a baseband modem in synchronization with a reception reference signal, using a sample synchronization manager to generate both transmission and reception reference signals, thereby addressing latency and synchronization challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If an analog interface is used between RFIC and baseband modem, then bandwidth requirements are satisfied, but chip manufacturing costs increase due to excessive number of pins
Solution Approach 1:
The patent replaces the analog interface (mechanical/electrical connection system with multiple pins) with a digital interface that uses fewer pins. The digital interface transmits data in a serialized format, reducing the physical connection requirements while maintaining bandwidth through efficient data encoding and timing synchronization mechanisms.
2Ease of manufacture
If a digital interface is used between RFIC and baseband modem, then chip manufacturing costs are reduced, but latency vacillates based on variable timing factors
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the clock signals between RFIC and baseband modem before data transmission begins. The system establishes a reference clock relationship and uses predetermined timing patterns to ensure that data arrives at the expected time, eliminating latency variations caused by timing jitter.
Solution Approach 2:
The patent implements feedback mechanisms where the receiving end monitors the timing of incoming data frames and adjusts its clock recovery process accordingly. This closed-loop timing synchronization ensures that latency remains consistent even when environmental factors cause minor variations in signal propagation.
3Ease of manufacture
If a digital interface is used between RFIC and baseband modem, then chip manufacturing costs are reduced, but RF band-to-baseband synchronization performance deteriorates
Solution Approach 1:
The patent makes the digital interface multi-functional by designing it to simultaneously handle data transmission and timing synchronization. The same digital communication channel that reduces pin count also carries embedded timing reference signals and synchronization markers, allowing the system to maintain reliable RF-to-baseband synchronization without requiring separate dedicated synchronization hardware.
Data Source
AI summary
A baseband IC for performing digital communication with an RFIC and a device including the same. The baseband IC for performing digital communication with an RFIC includes a digital interface circuit configured to receive a frame signal including at least one sampled signal from the RFIC according to a digital interface protocol, reconstruct the at least one sampled signal from the frame signal, and transfer the reconstructed sampled signal to a baseband modem in synchronization with a reception reference signal, and a sample synchronization manager configured to generate the reception reference signal, wherein the frame signal is transmitted from the RFIC to the baseband IC in synchronization with a transmission reference signal.