Baseband Processor DVFS for Power Saving
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Solution Overview
Problem
Current mobile devices face challenges in power efficiency, particularly in baseband processing, where high clock rates and supply voltages lead to significant power consumption, necessitating a method to dynamically adjust these parameters to reduce power usage without compromising processing performance.
Innovation Solution
A baseband processing method and processor that adjust clock rate and supply voltage based on the number of granted resource blocks in a downlink signal, using dynamic voltage and frequency scaling (DVFS) and pre-defined settings from a lookup table to ensure real-time processing while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high clock rate and supply voltage are used for baseband processing, then processing performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling (DVFS) that adjusts clock rate and supply voltage based on real-time baseband processing load. The system transitions from static high-performance settings to dynamic adaptation, matching power consumption to actual processing requirements. This resolves the contradiction by making performance and power consumption variable rather than fixed at high levels.
Solution Approach 2:
The patent changes the operating parameters (clock rate and supply voltage) of the baseband processor based on detected DL grant information and resource block allocations. By varying these parameters according to actual processing needs rather than maintaining constant high values, the system achieves both performance requirements and power savings.
2Use of energy by moving object
If clock rate and supply voltage are reduced to save power, then power consumption decreases, but processing performance deteriorates
Solution Approach 1:
The system uses feedback from decoded DL grant information and resource block detection to dynamically adjust clock rate and voltage. This closed-loop control ensures that processing performance is maintained at adequate levels while minimizing power consumption, resolving the contradiction between power savings and performance maintenance.
Solution Approach 2:
The patent performs preliminary decoding of control sections and detection of DL grant information before adjusting baseband processing parameters. This advance preparation allows the system to set appropriate clock rates and voltages in advance, ensuring performance requirements are met while avoiding unnecessary high-power operation.
3Use of energy by moving object
If dynamic voltage and frequency scaling is implemented, then power efficiency is improved, but system complexity increases
Solution Approach 1:
The baseband processor performs self-adjustment of clock rate and voltage based on its own processing load and detected DL grant information. This self-service capability reduces the need for external power management control, simplifying the overall system while improving power efficiency through autonomous DVFS operation.
Data Source
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AI summary
The disclosure relates to a baseband processing method, comprising: receiving a downlink (DL) baseband (BB) signal in a transmission time interval (TTI), wherein the DL BB signal comprises a time-frequency resource comprising a control section and a data section; decoding at least part of the control section to detect a DL grant information; if the DL grant information is detected, determine a number of granted data resource blocks from the DL grant information; and adjust at least one of a clock rate and supply voltage of the baseband processing based on the number of granted resource blocks.