Baseline Compensation Circuit for Magnetic Storage Signal Recovery
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Solution Overview
Problem
In perpendicular recording scenarios, the use of high pass filters in data detection systems leads to the loss of low frequency information, resulting in a lower signal-to-noise ratio due to the elimination of DC and low frequency components, which is not effectively addressed by existing error feedback methods that rely on detected data bits, causing latency issues.
Innovation Solution
The implementation of a data processing system that includes a preamplifier, analog-to-digital converter, data detector, and baseline compensation module, which amplifies the input signal, converts it to a digital signal, and uses a baseline compensation module to calculate and aggregate a compensation factor to restore low frequency energy by modifying the pole of a low pass filter, thereby mitigating the effects of high pass filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high pass filter is used in the preamplifier to allow fast write to read recovery, then the write to read recovery speed is improved, but low frequency information including DC components is lost
Solution Approach 1:
The patent segments the signal processing into two independent paths: the main high pass filtered path for fast write-to-read recovery, and a separate low frequency path that captures DC and low frequency components. These paths are processed independently and then recombined, allowing both fast recovery and information preservation without interference between the functions
Solution Approach 2:
The patent introduces an intermediary summation node that combines the high pass filtered signal with the low frequency compensated signal. This intermediary element allows the two signal paths to coexist and be merged, enabling the system to benefit from both the fast recovery characteristics of the high pass filter and the information preservation of the low frequency path
2Loss of information
If error feedback signal is derived from detected bits to drive spectrum mismatch compensation, then lower frequency information is preserved, but latency increases
Solution Approach 1:
The patent performs preliminary action by capturing and accumulating low frequency components directly from the analog signal path before digital detection and error feedback processing. The baseline compensation is accumulated in the analog domain using a summation node that integrates low frequency content in real-time, eliminating the need to wait for detected bit feedback and thus reducing latency while preserving low frequency information
Solution Approach 2:
The patent replaces the mechanical feedback loop that relies on detected bits with an electronic/continuous accumulation mechanism in the analog domain. Instead of using a digital feedback system that requires complete detection cycles, the system uses continuous analog integration to capture low frequency content, substituting a faster electronic process for the slower mechanical feedback loop
3Speed
If high pass filter eliminates DC and low frequency energy, then fast write to read recovery is achieved, but signal to noise ratio decreases
Solution Approach 1:
The patent merges two previously separate signal paths: the high pass filtered signal path that provides fast write-to-read recovery, and the low frequency signal path that preserves DC and low frequency components. By combining these paths through a summation node, the system achieves both fast recovery speed and improved signal-to-noise ratio, as the low frequency components contribute additional signal energy without interfering with the recovery characteristics
Data Source
AI summary
Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, some embodiments provide data processing circuits that include: an input circuit, a processing circuit, a data detection circuit, and a baseline compensation circuit. The input circuit receives a first data input and provides a second data input. The input circuit excludes low frequency energy exhibited in the first data input from the second data input. The processing circuit generates a representation of the second data input, and the data detection circuit generates a representation of the first data input based at least in part on the representation of the second data input. The baseline compensation circuit calculates an accumulated difference between the representation of the first data input and the representation of the second data input across a number of bit periods, and calculates a compensation factor based at least in part on the accumulated difference.