Batch Component Carrier Lamination via Segmented Wafer Merging
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Solution Overview
Problem
Existing methods of manufacturing component carriers are complex and require significant effort, lacking efficiency in producing reliable carriers with high-density integrated circuits and miniaturized packaging.
Innovation Solution
A method involving the simultaneous lamination of separate wafer structures with electrically conductive and insulating layers, followed by singularization into component carriers, and arranging electronic components on a common panel with redistribution layers to form efficient batch manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods of manufacturing component carriers are used, then reliable component carriers can be produced, but the manufacturing process is complex and requires significant effort
Solution Approach 1:
The manufacturing process is segmented into distinct modules: providing separate wafer structures with electronic components, simultaneously laminating multiple layer structures (conductive and insulating), and singularizing the laminated structure into individual component carriers. This segmentation allows each module to be optimized independently while maintaining overall reliability.
Solution Approach 2:
Multiple manufacturing operations are merged into a single simultaneous lamination step where wafer structures, conductive layer structures, and insulating layer structures are laminated together in one process. This combines multiple sequential steps into a unified operation, reducing process complexity while ensuring reliable integration of all components.
2Productivity
If existing methods of manufacturing component carriers are used, then component carriers can be produced, but the manufacturing process requires significant effort
Solution Approach 1:
Wafer structures with electronic components are prepared in advance before the lamination process. The electronic components are pre-positioned on the wafer structures, and the conductive and insulating layer structures are prepared separately. This preliminary preparation allows the actual lamination and singularization steps to be performed more efficiently with reduced manufacturing effort.
Solution Approach 2:
The simultaneous lamination of wafer structures, conductive layer structures, and insulating layer structures combines multiple manufacturing operations into one unified process step. This merging eliminates the need for separate lamination steps for each layer type, significantly reducing the total manufacturing effort while increasing production efficiency.
3Device complexity
If separate wafer structures are laminated simultaneously with multiple layer structures, then the manufacturing process is simplified, but precise alignment and integration must be maintained
Solution Approach 1:
By merging the lamination of wafer structures, conductive layer structures, and insulating layer structures into a single simultaneous operation, the process maintains simplicity while ensuring precise alignment. The simultaneous lamination ensures that all layers are bonded together in their correct relative positions without requiring multiple alignment steps.
Solution Approach 2:
The lamination process itself acts as an intermediary mechanism that simultaneously bonds multiple layer structures together with precise alignment. The lamination pressure and temperature conditions serve as controlling intermediaries that ensure the conductive and insulating layers are precisely positioned relative to the wafer structures during the bonding process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces material waste, and enables the production of reliable component carriers with embedded electronic components, enhancing efficiency and reducing thermal mismatch issues.
Implementation Method 1
simultaneously laminating the wafer structures with at least one electrically conductive layer structure and at least one electrically insulating layer structure
Data Source
AI summary
A method of manufacturing a batch of component carriers is disclosed. The method includes providing a plurality of separate wafer structures, each comprising a plurality of electronic components, simultaneously laminating the wafer structures with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and singularizing a structure resulting from the laminating into the plurality of component carriers, each comprising at least one of the electronic components, a part of the at least one electrically conductive layer structure and a part of the at least one electrically insulating layer structure.