Battery Management Chip Daisy Chain With Automatic Clock Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing daisy chain communication methods in battery management systems suffer from high communication power consumption and unsynchronized clocks, lacking effective communication anti-interference and signal recognition.
Innovation Solution
Implement a chip communication circuit with automatic clock synchronization using a sinusoidal sawtooth waveform for isolated communication between battery management chips, where clock synchronization information is embedded in control instructions to enable automatic synchronization and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing daisy chain communication methods are used, then communication between battery management chips is achieved, but communication power consumption is high
Solution Approach 1:
The patent implements periodic clock synchronization actions where the head battery management chip periodically sends synchronization instructions to downstream chips. This periodic synchronization mechanism ensures that all chips maintain synchronized clocks while operating in low-power modes between synchronization events, thereby reducing overall communication power consumption without compromising communication reliability.
2Reliability
If existing daisy chain communication methods are used, then data transmission is achieved, but clocks among battery management chips are unsynchronized
Solution Approach 1:
The patent introduces a head battery management chip as an intermediary that centralizes clock synchronization functionality. This head chip generates synchronized clock signals and distributes them to all downstream battery management chips through the existing daisy chain communication interface. This intermediary approach achieves clock synchronization without requiring complex distributed synchronization protocols across all chips, thereby maintaining reliability while controlling system complexity.
3Object-affected harmful factors
If universal asynchronous receiver/transmitter is used for conversion, then isolated serial communication is achieved, but communication anti-interference and signal recognition cannot be simultaneously optimized
Solution Approach 1:
The patent changes the signal waveform parameter from conventional rectangular waves to sinusoidal sawtooth waves for the daisy chain communication interface. This parameter change provides superior anti-interference characteristics because sinusoidal waves have smoother transitions and fewer high-frequency harmonics that could cause interference.同时, the well-defined characteristics of sinusoidal sawtooth waves make them easy to recognize and synchronize, resolving the contradiction between anti-interference and signal recognition.
Data Source
AI summary
The present application provides a chip communication circuit, method and apparatus based on automatic clock synchronization. The method includes: determining clock synchronization information of a first battery management chip in response to a received control instruction; replacing a chip selection enable signal in the control instruction with a clock synchronization signal carrying the clock synchronization information of the first battery management chip to obtain a new control instruction; and transmitting the new control instruction to other battery management chips, so that the other battery management chips perform automatic clock synchronization based on the clock synchronization information carried in the new control instruction; where the other battery management chips are battery management chips among the multiple battery management chips except for the first battery management chip, and a daisy chain with a sinusoidal sawtooth waveform is used for isolated communication between different battery management chips.