Battery Charge Discharge Control Circuit FET Gate Protection
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Solution Overview
Problem
In charge/discharge control circuits for secondary batteries, the voltage of control signals for FETs can exceed their gate breakdown voltages, leading to increased on-resistance and heat generation, particularly in multi-cell battery systems where low-cost FETs with low gate breakdown voltages are used.
Innovation Solution
A charge/discharge control circuit with a clamp voltage output circuit that outputs a voltage lower than the power supply voltage to the FET gate when the power supply voltage is high, and switches to output the power supply voltage when it drops below a prescribed level, preventing excessive voltage and reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage of control signals is set to match the power supply voltage to ensure sufficient FET turn-on, then the FET can be fully activated, but the gate breakdown voltage of the FET may be exceeded causing damage or increased on-resistance
Solution Approach 1:
The patent changes the voltage parameter of the control signal dynamically based on the power supply voltage level. When power supply voltage exceeds a predetermined threshold, the control signal voltage is clamped to a lower level (gate breakdown voltage or slightly higher) to prevent damage. When power supply voltage is at or below the threshold, the control signal voltage matches the power supply voltage for optimal FET turn-on. This parameter adaptation resolves the contradiction between FET safety and turn-on effectiveness.
Solution Approach 2:
The patent introduces a clamp circuit as an intermediary component between the control signal source and the FET gate. This clamp circuit mediates the voltage transfer by allowing full voltage transmission when safe, but limiting the voltage to a safe level when the power supply voltage is high. The clamp circuit thus enables the control system to achieve both full FET activation and gate protection without direct modification of the control logic.
2Reliability
If a clamp circuit is added to limit control signal voltage to prevent FET gate breakdown, then FET safety is improved, but the circuit complexity increases
Solution Approach 1:
The patent employs a simple clamp circuit using readily available components (such as Zener diodes or transistor-based voltage clamping) that are inexpensive and easy to integrate. Rather than using complex active control mechanisms or expensive specialized protection devices, the invention uses a straightforward voltage clamping approach that adds minimal complexity while providing effective FET gate protection. The simplicity of the clamp circuit design keeps the overall device complexity low.
3Reliability
If the control signal voltage is reduced to stay below gate breakdown voltage, then FET gate safety is maintained, but the on-resistance of the FET increases causing heat generation
Solution Approach 1:
The patent makes the control signal voltage dynamic rather than fixed. The voltage level adapts in real-time based on the power supply voltage condition. When power supply voltage is high, the control signal is clamped to a lower safe level to prevent gate breakdown. When power supply voltage is low (at or below threshold), the control signal voltage increases to match the power supply voltage, ensuring sufficient FET turn-on and low on-resistance. This dynamic adjustment eliminates the need to constantly operate with reduced voltage, thereby minimizing energy loss and heat generation while maintaining gate safety.
Data Source
AI summary
A charge/discharge control circuit includes a first power supply terminal connected to a first electrode of a secondary battery, and a discharge control output circuit which outputs a discharge control signal to a gate of a discharge control FET which controls discharging of the secondary battery. The discharge control output circuit includes a clamp voltage output circuit which outputs a clamp voltage lower than a voltage of the first power supply terminal to a discharge control terminal to turn on the discharge control FET when the voltage of the first power supply terminal is higher than a prescribed voltage, and a power supply voltage output circuit which outputs the voltage of the first power supply terminal to the discharge control terminal to turn on the discharge control FET when the voltage of the first power supply terminal is equal to or less than the prescribed voltage.