Battery Management Memory Access Control for Cache Consistency
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Solution Overview
Problem
Existing battery management systems face challenges in preventing data inconsistency in multi-core environments, particularly in battery packs and vehicles, due to high system resource requirements and slow data processing times, making them inefficient for rapid data processing needs.
Innovation Solution
A battery management apparatus and method that sets a main core and sub cores to manage data access, blocking sub core access to the main memory during data recording and initializing the cache memory to prevent data inconsistency, allowing efficient battery state estimation with minimal system resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a physical memory page is allocated to process data in a multi-core environment, then cache consistency is guaranteed, but system resources are heavily consumed and data processing time increases
Solution Approach 1:
The patent segments the multi-core system into a main core and sub cores, with the main core responsible for data consistency management. This segmentation allows the main core to control memory access permissions, preventing sub cores from accessing memory during critical updates while minimizing the need for full physical memory page allocations, thus reducing system resource consumption while maintaining cache consistency.
2Reliability
If data is processed in a physical memory page and then updated, then cache consistency is ensured, but data processing time increases
Solution Approach 1:
The patent applies preliminary action by having the main core block sub core access to memory before data processing begins. This prevents the need for subsequent memory synchronization operations, as sub cores cannot access or modify the data during the critical update period. This preliminary blocking action ensures cache consistency without requiring time-consuming memory page allocations and updates, significantly reducing data processing time.
3Productivity
If multiple cores access memory simultaneously without control, then data processing speed is fast, but data inconsistency occurs
Solution Approach 1:
The patent introduces the main core as an intermediary between sub cores and the memory system. The main core mediates memory access by granting or blocking permissions based on the current processing state. This intermediary mechanism allows sub cores to rapidly process data in parallel while the main core ensures data consistency by controlling when memory access is permitted, thus maintaining both high processing speed and data reliability.
Data Source
AI summary
A battery management apparatus according to an embodiment of the present disclosure includes a processor including a plurality of cores respectively provided with a cache memory and configured to set a core storing a record-target data in the cache memory thereof among the plurality of cores as a main core and set a core other than the main core among the plurality of cores as a sub core; and a main memory configured to store the record-target data by the main core, wherein the main core is configured to block an authority of the sub core to access the main memory while the record-target data is being recorded in the main memory, and endow an authority to access the main memory to the sub core after the record-target data is recorded in the main memory.