Battery Management NAND Gate Inspection for Defect Detection
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Solution Overview
Problem
Existing battery management systems struggle to detect defects in NAND gate circuits due to their input and output operation characteristics, which can lead to undetected abnormal power supply states.
Innovation Solution
A battery management module that includes a microcontroller unit, a comparator, and a NAND gate circuit, where the module is configured to output a low-level signal to the NAND gate circuit during an inspection mode, allowing the microcontroller to determine if the NAND gate circuit is defective based on its output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a logic circuit is used to detect overvoltage or undervoltage of battery cell voltage, then voltage monitoring function is achieved, but defects cannot be detected due to input and output operation characteristics of the logic circuit
Solution Approach 1:
The patent applies preliminary action by performing defect detection on the NAND gate circuit before the battery management system is deployed. The inspection mode is activated during manufacturing or testing phase, where the microcontroller outputs a predetermined low-level signal to the NAND gate circuit, and the expected high-level output is verified. This preliminary testing ensures defects are identified early, preventing undetected failures in the actual battery monitoring operation.
Solution Approach 2:
The patent uses inversion by reversing the normal operation conditions to test for defects. Instead of applying normal voltage signals and expecting normal logic outputs, the inspection mode applies a predetermined low-level signal to the input and expects a high-level signal at the output. This inverted testing approach exploits the NAND gate's logical properties to reveal defects that would not be apparent under normal operating conditions.
2Reliability
If normal operation mode is used, then battery management function is performed, but NAND gate circuit defects remain undetected
Solution Approach 1:
The patent implements dynamics by creating two distinct operational modes that can switch between them. The inspection mode is dynamically activated during manufacturing or testing, while the normal operation mode is used during actual battery management. This dynamic mode switching allows the system to adapt its behavior: in inspection mode, the microcontroller outputs predetermined low-level signals for defect detection, while in normal mode, it performs standard battery monitoring functions. The system can transition between these states as needed.
Solution Approach 2:
The patent applies segmentation by dividing the battery management system's operation into distinct functional segments: an inspection mode segment for defect detection and a normal operation mode segment for battery monitoring. This segmentation is achieved through mode indication signals that control which set of operations is active. The NAND gate circuit's output is routed differently in each mode: during inspection, it's monitored for defect detection; during normal operation, it's used for actual voltage threshold detection. This segmentation allows defect information to be captured without interfering with normal battery management functions.
Data Source
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AI summary
A battery management module (220, 400), including a microcontroller unit (228, 430), a first comparator (460) configured to compare an input signal with a first reference signal (464) and output a first comparison result and a NAND gate circuit (450) configured to receive a first input from the microcontroller unit (228, 430) and a second input that is the first comparison result from the first comparator (460) to generate an output signal, wherein, in an inspection mode, the first comparator (460) is connected to a battery module tester (500), the microcontroller unit (228, 430) outputs a low-level signal as the first input, the first comparator (460) receives the input signal from the battery module tester (500) and outputs a low-level signal as the first comparison result and the microcontroller unit (228, 430) is further configured to receive the output signal of the NAND gate circuit (450) and determine the NAND gate circuit (450) is defective in response to the output signal of the NAND gate circuit (450) being a low-level signal.