Battery PCB FET Layout for Uniform Current Sharing
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Solution Overview
Problem
Existing power supply devices with secondary battery cells experience uneven current distribution and thermal destruction due to structural restrictions, leading to excessive heating of semiconductor elements.
Innovation Solution
The power supply device incorporates a circuit board design with first and second terminal blocks, where semiconductor elements are arranged to minimize current concentration by using current impeding regions with varying electrical resistances and thermal vias to balance current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor elements are arranged in a limited area on the circuit board, then the device size is reduced, but current distribution becomes uneven causing thermal destruction
Solution Approach 1:
The patent applies local quality by introducing current impeding regions with different electrical resistances at specific locations on the circuit board. The first current impeding region has a first electrical resistance and the second current impeding region has a second electrical resistance, creating non-uniform local properties that compensate for the natural tendency of current to concentrate in shorter paths. This ensures uniform current distribution across all semiconductor elements even when they are arranged in a limited area.
2Device complexity
If current paths are made shorter to reduce device complexity, then current flow resistance decreases, but current concentration increases causing excessive heating
Solution Approach 1:
The patent changes the electrical resistance parameter of the current paths by introducing current impeding regions with specifically designed resistance values. The first current impeding region has a first electrical resistance and the second current impeding region has a second electrical resistance, which are optimized to balance the current distribution. This parameter adjustment compensates for the shorter path lengths and prevents current concentration and excessive heating.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration uniformly distributes current, preventing excessive heating and thermal destruction of semiconductor elements, ensuring safe and efficient operation.
Implementation Method 1
A first current path connecting the first semiconductor element and the second semiconductor element in series to each other is longer than a second current path connecting the third semiconductor element and the fourth semiconductor element in series to each other. The first current path includes a first current impeding region, disposed between the first semiconductor element and the second semiconductor element, configured to impede current flow. The second current path includes a second current impeding region, disposed between the third semiconductor element and the fourth semiconductor element, configured to impede current flow. A second electrical resistance of the second current impeding region is higher than a first electrical resistance of the first current impeding region.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Uneven distribution of current is suppressed even in a condition that semiconductor elements are mounted in a limited area on a circuit board. A power supply device includes a secondary battery cell, charging/discharging FETs (21-28), and a circuit board (30) including a first terminal block (31) and a second terminal block (32). A first charging/discharging FET (21) and a third charging/discharging FET (23) are disposed at a side of the first terminal block on circuit board (30). A second charging/discharging FET (22) and a fourth charging/discharging FET (24) are disposed at a side of the second terminal block on circuit board (30). A first current path (41) connecting the first charging/discharging FET (21) in series to the second charging/discharging FET (22) is longer than a second current path (42) connecting the third charging/discharging FET (23) in series to the fourth charging/discharging FET (24). The first current path (41) includes a first current impeding region (51) configured to impede current flow. The second current path (42) includes a second current impeding region (52) configured to impede current flow. A second electrical resistance (52R) of the second current impeding region (52) is higher than a first electrical resistance (51R) of the first current impeding region (51).