Battery Protection Package Vertical Stacking
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Solution Overview
Problem
Conventional battery protection ICs face challenges in reducing size and thickness due to wire bonding, which hinders the development of smaller and thinner battery protection packages.
Innovation Solution
The solution involves vertically stacking a power control IC on top of common-drain MOSFETs and embedding a majority of the power control IC and solder balls into a packaging layer, replacing bonding wires, and using a process that includes fabricating power control ICs, integrating them with MOSFETs, forming a packaging layer, and applying grinding processes to reduce thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If wire bonding is used for interconnection in battery protection IC, then electrical connection is achieved, but the package thickness increases due to the high loop of bonding wire
Solution Approach 1:
The patent transitions from planar wire bonding to vertical stacking architecture, where the power control IC is positioned directly above the MOSFETs in the Z-dimension. This dimensional change eliminates the need for bonding wires extending outward, thereby reducing package thickness while maintaining electrical connectivity through vertical vias and contact holes.
Solution Approach 2:
The patent removes the bonding wire interconnection structure entirely from the package design. By extracting this element and replacing it with direct vertical electrical paths through the substrate and packaging layers, the design eliminates the thickness contribution of bonding wire loops while simplifying the overall interconnection architecture.
2Area of stationary object
If conventional battery protection IC structure is used with power control IC and dual common-drain MOSFETs co-packed in lead frame, then functional requirements are met, but the package size is limited to minimum footprint of 2 mm×4 mm
Solution Approach 1:
The patent employs vertical stacking to arrange the power control IC and MOSFETs in multiple layers along the Z-axis, transforming a planar 2D layout into a 3D structure. This allows the package footprint to be reduced to 1.6 mm×2 mm while accommodating all functional components through vertical integration, thereby achieving smaller area without sacrificing design capability.
Solution Approach 2:
The patent implements a nested arrangement where the power control IC is positioned above and interconnected with the MOSFETs through vertical electrical paths. This nesting approach allows compact integration of multiple functional blocks within a minimal footprint, enabling the package to maintain full functionality while achieving a reduced 1.6 mm×2 mm area.
3Volume of stationary object
If silicon substrate size is reduced to minimize package size, then package compactness is improved, but drain-source on resistance increases
Solution Approach 1:
The patent applies local quality optimization by selectively positioning the MOSFET active regions and interconnection paths to maximize current flow efficiency. The vertical stacking architecture creates direct, short current paths from source to drain through minimized resistance zones, allowing reduced silicon substrate area while maintaining low drain-source on resistance through optimized local current distribution.
Solution Approach 2:
By transitioning to vertical stacking, the patent creates three-dimensional current paths that reduce the effective current flow distance through the silicon substrate. The vertical interconnection structure provides direct electrical pathways that minimize resistance even with reduced substrate area, thereby maintaining reliability while achieving compact 1.6 mm×2 mm packaging.
4Volume of stationary object
If power control IC die size is reduced to minimize package size, then package compactness is improved, but power consumption increases
Solution Approach 1:
The patent optimizes local quality by precisely positioning the power control IC die to minimize interconnection path lengths to the MOSFETs. The vertical stacking architecture creates short, direct electrical paths that reduce resistive losses and switching losses, allowing the use of smaller IC dies without increasing power consumption. The localized optimization of interconnection geometry compensates for the reduced die size.
Solution Approach 2:
The vertical stacking architecture reduces the horizontal interconnection distances that would otherwise require larger IC die areas. By moving connections into the vertical dimension through direct vias and contact holes, the patent enables smaller power control IC dies while maintaining efficient electrical paths that minimize power consumption through reduced resistance and capacitance.
Data Source
AI summary
The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.