Baud Rate Clock Generation With Delay Regulation for Serial Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In asynchronous serial interface communications, it is challenging to set the Baud rate of receiver and transmitter devices to be similar, leading to data reception/transmission errors due to the difficulty in transforming high-speed oscillators into low-speed Baud rates accurately.
Innovation Solution
A clock generating device comprising a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit, which outputs a reference clock signal, counts cycles to generate clock signals, and uses a delay regulator circuit to adjust the output, thereby minimizing errors in Baud rate generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-speed oscillator is transformed into a low-speed Baud rate using a conventional Baud rate generator, then the Baud rate is generated, but the precision and accuracy of the Baud rate are insufficient leading to data transmission errors
Solution Approach 1:
The patent divides the Baud rate generation process into multiple independent modules: a first counter for initial division, a second counter for further division, and a delay regulator circuit for fine-tuning. This segmentation allows each module to be optimized independently, improving overall precision while maintaining reliability through modular error control.
Solution Approach 2:
The patent introduces dynamic adjustment mechanisms including the delay regulator circuit that can dynamically adjust the output clock signal based on detected timing differences, and configurable counter presets that allow adaptive Baud rate generation. This dynamic capability enables the system to maintain high precision under varying transmission conditions.
2Ease of operation
If the Baud rate of receiver and transmitter devices is set manually in asynchronous serial interface communications, then the configuration is simple, but it is difficult to set the Baud rates to be similar resulting in data reception/transmission errors
Solution Approach 1:
The patent implements a feedback mechanism where the delay regulator circuit continuously monitors the timing of received data and adjusts the Baud rate generator accordingly. This closed-loop feedback automatically compensates for Baud rate mismatches between transmitter and receiver, eliminating the need for precise manual configuration while maintaining high matching precision.
Solution Approach 2:
The Baud rate generator performs self-calibration by detecting timing errors in received data and automatically adjusting its own parameters. This self-service capability allows the system to automatically achieve precise Baud rate synchronization without requiring expert manual configuration, combining ease of operation with high precision.
3Manufacturing precision
If a conventional Baud rate generator is used without delay regulation, then the device complexity is low, but the Baud rate accuracy is insufficient leading to transmission errors
Solution Approach 1:
The patent employs a nested structure where the delay regulator circuit is integrated within the clock generating device, and the second counter is nested within the first counter's output stage. This nesting allows the additional precision components to be tightly integrated without proportionally increasing overall device complexity, achieving high Baud rate accuracy with efficient resource utilization.
Data Source
AI summary
A clock generating device includes a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first number of cycles of the reference clock signal and generates a first count. The first counter outputs a first clock signal according to the first count and the divisor. The second counter counts a second number of cycles of the first clock signal and generates a second count. The second counter outputs a second clock signal according to the second count and a coefficient. The delay regulator circuit determines whether to control the first counter to delay outputting the first clock signal according to the first clock signal.