Baud-Rate CDR and CTLE Control Using Adaptive Reference Voltages
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Solution Overview
Problem
There is a need for a system and method to effectively control the parameters of clock and data recovery circuits (CDR) and continuous time linear equalizers (CTLE) in serial data transmission, particularly in baud-rate receivers, which often rely on reference voltages that require precise adjustment to optimize data recovery and equalization.
Innovation Solution
The proposed solution involves a circuit with multiple samplers and reference voltage control mechanisms that adjust reference voltages based on input signal samples, using pattern filters and accumulators to adapt decision feedback equalizer coefficients and control parameters of the CTLE, ensuring optimal clock and data recovery without the need for phase interpolators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If baud-rate receivers use single clock phase for data recovery, then device complexity is reduced by eliminating phase interpolators, but measurement precision of sampling timing deteriorates
Solution Approach 1:
The patent changes the reference voltage parameter dynamically based on detected bit patterns. By adjusting the reference voltage level according to the sequence of received bits, the system compensates for the reduced sampling precision inherent in single-phase baud-rate recovery, thereby maintaining reliable data detection without requiring complex multi-phase clock circuits
Solution Approach 2:
The system implements feedback by using the detected bit patterns to control the reference voltage adjustment. The detection of specific bit sequences provides feedback information that drives the adaptive reference voltage modification, enabling the receiver to compensate for timing errors and maintain accurate data recovery despite using a simplified single-clock-phase architecture
2Adaptability or versatility
If reference voltages are controlled by other circuits, then adaptability of the receiver is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The receiver performs self-adjustment by automatically detecting bit patterns in the incoming data stream and autonomously modifying its own reference voltage parameter. This self-service mechanism eliminates the need for external control circuits or separate adaptation systems, achieving high receiver adaptability while maintaining simple device architecture
Solution Approach 2:
The single clock phase circuit performs multiple functions: it serves as both the sampling clock and the timing reference for data recovery. By making the clock circuit multi-functional, the system achieves versatile data recovery capability without requiring additional dedicated control circuits, thereby balancing adaptability with circuit simplicity
Data Source
AI summary
A circuit for receiving serial data. In some embodiments, the circuit has an input for receiving an analog input signal, and includes a first sampler for sampling the analog input signal relative to a first reference voltage, a second sampler for sampling the analog input signal relative to a second reference voltage, and a reference voltage control circuit. The second reference voltage may have a sign opposite to that of the first reference voltage; and the reference voltage control circuit may be configured to adjust the first reference voltage or the second reference voltage, based on a first sample of the analog input signal, the first sample having been taken at a sampling time corresponding to a one bit, in the serial data, preceded by a one bit and followed by a one bit.