Baud-Rate Clock Recovery with Partial Response Equalization
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Solution Overview
Problem
Current data exchange technologies face inefficiencies in high-speed serial links, particularly in baud rate clock recovery, leading to suboptimal data transfer rates and signal integrity issues in applications like computer servers and internet services.
Innovation Solution
A clock data recovery system employing 2-tap partial response equalization with baud rate clock recovery, utilizing high-pass filters, clocked-data and error comparators, decision feedback equalization, and digital filters to lock phase at +/-h2, enabling efficient data exchange across high-speed serial links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional clock recovery methods are used in high-speed serial links, then device complexity is reduced, but data transfer efficiency and signal integrity deteriorate
Solution Approach 1:
The system segments the clock recovery function into multiple specialized components: a high-pass filter to remove DC components, clocked comparators to sample at optimal moments, and digital filters to reconstruct the clock signal. This segmentation allows each component to be optimized for its specific function, improving overall data transfer efficiency while managing complexity through modular design.
Solution Approach 2:
The patent introduces intermediate processing stages between the incoming serial data and the recovered clock signal. Clocked comparators act as intermediaries to capture signal transitions at precise moments, and digital filters serve as intermediaries to synthesize the clock waveform. These intermediary elements improve signal integrity and transfer efficiency by systematically addressing distortion and timing issues.
2Reliability
If baud rate clock recovery is implemented, then signal integrity improves, but device complexity increases
Solution Approach 1:
The system performs preliminary filtering of the incoming signal through a high-pass filter before clock recovery operations. This preliminary action removes DC components and low-frequency distortions that would otherwise degrade signal integrity. By preparing the signal in advance, the subsequent clock recovery stages can operate more effectively without being burdened by these pre-existing distortions.
Solution Approach 2:
The patent implements feedback mechanisms where the recovered clock signal is used to control the timing of comparators and sampling operations. This feedback ensures that the system continuously adjusts to maintain optimal sampling points, thereby preserving signal integrity even in the presence of variations in data patterns or channel conditions. The feedback loop creates a self-correcting system that maintains reliability.
Data Source
AI summary
A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at a second post cursor; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.