Baud Rate Tracking Without Training Sequence

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Solution Overview

Problem

Existing UART communication techniques require prior knowledge of transmission timing and training sequence patterns for baud rate determination, limiting flexibility and efficiency in data recovery.

Innovation Solution

An apparatus and method utilizing a sampling circuit, clock counting circuit, bit counting circuit, and calculation circuit to track and compensate for baud rates without a training sequence, by sampling reception signals, counting clock cycles and bits, and updating bit cycles based on calculation values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If baud rate determination is performed using training sequence in prior art, then baud rate can be determined, but both receiver and transmitter must possess prior information of transmission timing and training sequence pattern

Engineering Contradiction:
Improvebaud rate determination accuracyVSAvoidprior information requirement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts and eliminates the requirement for training sequence from the baud rate determination process. By using transition detection and clock cycle counting on ordinary data bits instead of dedicated training sequences, the system removes the need for pre-shared pattern information while maintaining baud rate tracking capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The receiver performs self-service baud rate calibration by automatically detecting transitions in the received signal and calculating baud rate from clock cycle counts. The system uses its own local clock and transition detection capability to determine the transmitter's baud rate without external assistance or pre-programmed training sequences

Inventive Principle:
Principle #25Self-service

2Ease of operation

If baud rate calibration is performed using training sequence in prior art, then receiver can calibrate itself, but communication initialization requires negotiation of initial baud rate

Engineering Contradiction:
Improvereceiver self-calibration capabilityVSAvoidcommunication initialization time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The invention performs preliminary baud rate tracking and calibration actions continuously during data reception. Instead of waiting for initialization negotiation and then calibrating, the system continuously monitors transitions and updates baud rate estimates, making the calibration happen in advance and continuously rather than as a separate initialization step

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The baud rate tracking and calibration is performed continuously during normal data reception by continuously detecting transitions and updating clock cycle counts. This continuous calibration approach replaces the discrete initialization-time calibration with an ongoing process that maintains accurate baud rate tracking throughout communication

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS10511464B2Baud rate tracking and compensation apparatus and method
Publication Date: 2019.12.17 REALTEK SEMICON CORP
  • US10511464B2 patent drawing
  • US10511464B2 patent drawing
  • US10511464B2 patent drawing

AI summary

Disclosed is a baud rate tracking and compensation apparatus comprising: a clock generating component generating a clock; a sampling circuit sampling a reception signal according to the clock and thereby generating a sampled result, and the sampling circuit generating a transition notification signal when the sampled result indicates a transition of the reception signal; a clock counting circuit counting cycles of the clock between a first transition of the reception signal and a second transition of the reception signal according to the clock and the transition notification signal; a bit counting circuit counting bit(s) between the first transition and the second transition according to the clock and a bit cycle; and a calculation circuit dividing the number of the cycles by the number of the bit(s) to obtain a calculation value, and then updating the bit cycle according to the calculation value.