BBUL Carrier Grid Array Reduces Z-Height and Inductance
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Solution Overview
Problem
Microelectronic packaging technologies face challenges in reducing the z-height of combined device structures while maintaining effective electrical connectivity and thermal expansion mismatch reduction, especially in package-on-package configurations.
Innovation Solution
The implementation of Bumpless Build-Up Layer (BBUL) technology with a build-up carrier and conductive posts forming a grid array, eliminating solder bumps and providing direct contact between the die and carrier, along with additional routing contacts for interconnectivity, allows for reduced package height and improved thermal and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If package-on-package configuration is used to conserve space, then area utilization is improved, but z-height increases
Solution Approach 1:
The patent combines multiple functions into a single integrated carrier structure. The build-up carrier integrates the substrate, interconnection layers, and routing contacts into one unified component, eliminating the need for separate packaging layers and reducing overall z-height while maintaining area utilization benefits.
Solution Approach 2:
The patent transitions from traditional vertical stacking (increasing z-height) to a planar integration approach within the carrier. By routing interconnections laterally through the build-up layers and using grid array contacts at the same level, the design reduces reliance on vertical space while achieving package-on-package density.
2Reliability
If solder bumps are used for die-to-substrate connection, then electrical connectivity is achieved, but manufacturing complexity and stress increase
Solution Approach 1:
The patent extracts and eliminates the solder bump interconnection layer from the traditional packaging architecture. By using a bumpless build-up carrier with direct grid array contacts bonding to die contacts, the design removes the complex soldering process while maintaining reliable electrical connectivity between die and substrate.
Solution Approach 2:
The build-up carrier serves as an intermediary structure that provides direct mechanical and electrical bonding between the die and the external world. The carrier's grid array contacts directly bond to die contacts, eliminating the need for solder bumps as an intermediate connection layer and reducing thermal expansion mismatch stress.
3Reliability
If traditional flip-chip interconnection is used, then electrical connectivity is achieved, but package inductance increases
Solution Approach 1:
The patent segments the interconnection path into multiple thin build-up layers with distributed routing contacts, rather than using a single long flip-chip interconnect. This segmentation creates shorter, more distributed current paths through the carrier, reducing overall package inductance while maintaining electrical connectivity.
Solution Approach 2:
The patent changes the interconnection geometry from the vertical flip-chip approach to a lateral routing approach within the build-up layers. By routing signals horizontally through the carrier and using grid array contacts at the periphery, the design reduces the loop area and inductance compared to traditional flip-chip interconnection.
Data Source
AI summary
An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.