BBUL Package MEMS Integration in Carrier Voids
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Solution Overview
Problem
Microelectromechanical systems (MEMS) devices face limitations in real estate and scalability due to the integration of mechanical and electrical elements on a common silicon substrate, and existing packaging technologies like flip-chip interconnections lead to stress and reduced input/output performance.
Innovation Solution
The integration of MEMS devices within a bumpless build-up layer (BBUL) package architecture, where MEMS devices are embedded in the carrier's voids, eliminating the need for solder bumps and allowing direct contact between the die and carrier, enabling increased scalability without sacrificing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MEMS devices are integrated on a common silicon substrate with electrical elements, then mechanical and electrical functionality is achieved, but real estate availability and device scalability are limited
Solution Approach 1:
The patent transitions from two-dimensional integration on a silicon substrate to three-dimensional integration within the package body. MEMS devices are positioned in voids at different levels within the package, utilizing vertical space rather than horizontal substrate area. This dimensional shift enables multiple MEMS devices to coexist without competing for limited silicon real estate, thereby improving scalability while maintaining functional integration.
2Reliability
If flip-chip interconnections are used for packaging, then electrical connection is achieved, but thermal stress and package inductance increase
Solution Approach 1:
The patent extracts and eliminates the problematic flip-chip interconnection layer from the package architecture. By removing the solder bump interconnections entirely, the source of thermal stress (CTE mismatch between die and substrate) and package inductance is eliminated. The die is instead directly mounted to the carrier, creating a bumpless build-up layer structure that maintains electrical connectivity without the harmful intermediate interconnection layer.
3Strength
If solder bumps are used for die attachment, then mechanical connection is achieved, but assembly complexity and stress on low-k interlayer dielectric increase
Solution Approach 1:
The patent removes the solder bump attachment mechanism from the packaging process. The die is directly bonded to the carrier substrate without intermediate solder bumps, eliminating the complex multi-step assembly process involving bump formation, alignment, and reflow soldering. This direct attachment method reduces assembly complexity while maintaining mechanical strength and eliminating stress on the low-k interlayer dielectric.
Data Source
AI summary
An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die; and at least one device within the build-up carrier disposed in an area void of a layer of patterned conductive material. A method and an apparatus including a computing device including a package including a microprocessor are also disclosed.